From b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 21 Jul 2017 19:32:31 +0200 Subject: Fix handling of empty cell port assignments (i.e. ignore them) --- passes/techmap/techmap.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'passes/techmap/techmap.cc') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index e85714b57..ae89453d0 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -247,6 +247,9 @@ struct TechmapWorker continue; } + if (GetSize(it.second) == 0) + continue; + RTLIL::Wire *w = tpl->wires_.at(portname); RTLIL::SigSig c, extra_connect; -- cgit v1.2.3