From 661fa5ff92f19675cfd87754a99d0c5c42c9df13 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 2 Nov 2022 17:45:46 +0100 Subject: simplemap: Map `$xnor` to `$_XNOR_` cells The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of the `$_XNOR_` cell. --- passes/techmap/simplemap.cc | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'passes/techmap/simplemap.cc') diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f75b82919..baae8c6af 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -61,25 +61,11 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool()); - if (cell->type == ID($xnor)) - { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y)); - - for (int i = 0; i < GetSize(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - gate->setPort(ID::A, sig_t[i]); - gate->setPort(ID::Y, sig_y[i]); - } - - sig_y = sig_t; - } - IdString gate_type; if (cell->type == ID($and)) gate_type = ID($_AND_); if (cell->type == ID($or)) gate_type = ID($_OR_); if (cell->type == ID($xor)) gate_type = ID($_XOR_); - if (cell->type == ID($xnor)) gate_type = ID($_XOR_); + if (cell->type == ID($xnor)) gate_type = ID($_XNOR_); log_assert(!gate_type.empty()); for (int i = 0; i < GetSize(sig_y); i++) { -- cgit v1.2.3 From 7203ba7bc1d83777bd2c2c347d45209d8e3d4b84 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 2 Nov 2022 17:12:51 +0100 Subject: Add bitwise `$bweqx` and `$bwmux` cells The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals. --- passes/techmap/simplemap.cc | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) (limited to 'passes/techmap/simplemap.cc') diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index baae8c6af..11692b715 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -58,14 +58,17 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_b = cell->getPort(ID::B); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); - sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); - sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool()); + if (cell->type != ID($bweqx)) { + sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); + sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool()); + } IdString gate_type; - if (cell->type == ID($and)) gate_type = ID($_AND_); - if (cell->type == ID($or)) gate_type = ID($_OR_); - if (cell->type == ID($xor)) gate_type = ID($_XOR_); - if (cell->type == ID($xnor)) gate_type = ID($_XNOR_); + if (cell->type == ID($and)) gate_type = ID($_AND_); + if (cell->type == ID($or)) gate_type = ID($_OR_); + if (cell->type == ID($xor)) gate_type = ID($_XOR_); + if (cell->type == ID($xnor)) gate_type = ID($_XNOR_); + if (cell->type == ID($bweqx)) gate_type = ID($_XNOR_); log_assert(!gate_type.empty()); for (int i = 0; i < GetSize(sig_y); i++) { @@ -270,6 +273,23 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) } } +void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell) +{ + RTLIL::SigSpec sig_a = cell->getPort(ID::A); + RTLIL::SigSpec sig_b = cell->getPort(ID::B); + RTLIL::SigSpec sig_s = cell->getPort(ID::S); + RTLIL::SigSpec sig_y = cell->getPort(ID::Y); + + for (int i = 0; i < GetSize(sig_y); i++) { + RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); + gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->setPort(ID::A, sig_a[i]); + gate->setPort(ID::B, sig_b[i]); + gate->setPort(ID::S, sig_s[i]); + gate->setPort(ID::Y, sig_y[i]); + } +} + void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::SigSpec sig_a = cell->getPort(ID::A); @@ -395,6 +415,7 @@ void simplemap_get_mappers(dict mappers[ID($or)] = simplemap_bitop; mappers[ID($xor)] = simplemap_bitop; mappers[ID($xnor)] = simplemap_bitop; + mappers[ID($bweqx)] = simplemap_bitop; mappers[ID($reduce_and)] = simplemap_reduce; mappers[ID($reduce_or)] = simplemap_reduce; mappers[ID($reduce_xor)] = simplemap_reduce; @@ -408,6 +429,7 @@ void simplemap_get_mappers(dict mappers[ID($ne)] = simplemap_eqne; mappers[ID($nex)] = simplemap_eqne; mappers[ID($mux)] = simplemap_mux; + mappers[ID($bwmux)] = simplemap_bwmux; mappers[ID($tribuf)] = simplemap_tribuf; mappers[ID($bmux)] = simplemap_bmux; mappers[ID($lut)] = simplemap_lut; -- cgit v1.2.3