From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 16:38:54 +0200 Subject: Renamed port access function on RTLIL::Cell, added param access functions --- passes/techmap/dfflibmap.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/techmap/dfflibmap.cc') diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index ffe241182..7712d18b9 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) } else if (port.second != 0) log_abort(); - new_cell->set("\\" + port.first, sig); + new_cell->setPort("\\" + port.first, sig); } stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++; -- cgit v1.2.3