From 84bf862f7c58c2b69babf043ff5032f924a3ee4d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 14 Aug 2015 10:56:05 +0200
Subject: Spell check (by Larry Doolittle)
---
passes/sat/eval.cc | 6 +++---
passes/sat/expose.cc | 4 ++--
passes/sat/freduce.cc | 10 +++++-----
passes/sat/miter.cc | 2 +-
passes/sat/sat.cc | 2 +-
5 files changed, 12 insertions(+), 12 deletions(-)
(limited to 'passes/sat')
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index d97fa6f16..522664032 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -87,7 +87,7 @@ struct BruteForceEquivChecker
BruteForceEquivChecker(RTLIL::Module *mod1, RTLIL::Module *mod2, bool ignore_x_mod1) :
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
- log("Checking for equivialence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
+ log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
for (auto &w : mod1->wires_)
{
RTLIL::Wire *wire1 = w.second;
@@ -421,7 +421,7 @@ struct EvalPass : public Pass {
log_error("Can't find module `%s'!\n", mod2_name.c_str());
BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
- log_cmd_error("Modules are not equivialent!\n");
+ log_cmd_error("Modules are not equivalent!\n");
log("Verified %s = %s (using brute-force check on %d cases).\n",
mod1_name.c_str(), mod2_name.c_str(), checker.counter);
return;
@@ -594,7 +594,7 @@ struct EvalPass : public Pass {
log("\n");
if (undef.size() > 0) {
undef.sort_and_unify();
- log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef));
+ log("Assumed undef (x) value for the following signals: %s\n\n", log_signal(undef));
}
}
}
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 3d2bcf63a..ca784890b 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -237,8 +237,8 @@ struct ExposePass : public Pass {
log(" signal path at that wire.\n");
log("\n");
log(" -shared\n");
- log(" only expose those signals that are shared ammong the selected modules.\n");
- log(" this is useful for preparing modules for equivialence checking.\n");
+ log(" only expose those signals that are shared among the selected modules.\n");
+ log(" this is useful for preparing modules for equivalence checking.\n");
log("\n");
log(" -evert\n");
log(" also turn connections to instances of other modules to additional\n");
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index f9d3a82a5..e0d11243b 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -457,7 +457,7 @@ struct PerformReduction
out_depth[idx] = std::numeric_limits<int>::max();
if (verbose_level >= 1) {
- log("%s Found %d equivialent signals:", indt, int(bucket.size()));
+ log("%s Found %d equivalent signals:", indt, int(bucket.size()));
for (int idx : bucket)
log("%s%s%s", idx == bucket.front() ? " " : ", ", out_inverted[idx] ? "~" : "", log_signal(out_bits[idx]));
log("\n");
@@ -506,7 +506,7 @@ struct PerformReduction
std::vector<RTLIL::SigBit> r_sigbits;
for (int idx : r)
r_sigbits.push_back(out_bits[idx]);
- log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(r_sigbits));
+ log(" Found group of %d equivalent signals: %s\n", int(r.size()), log_signal(r_sigbits));
}
std::vector<int> undef_slaves;
@@ -692,7 +692,7 @@ struct FreduceWorker
if (!dump_prefix.empty())
dump();
- log(" Rewiring %d equivialent groups:\n", int(equiv.size()));
+ log(" Rewiring %d equivalent groups:\n", int(equiv.size()));
int rewired_sigbits = 0;
for (auto &grp : equiv)
{
@@ -766,7 +766,7 @@ struct FreducePass : public Pass {
log(" freduce [options] [selection]\n");
log("\n");
log("This pass performs functional reduction in the circuit. I.e. if two nodes are\n");
- log("equivialent, they are merged to one node and one of the redundant drivers is\n");
+ log("equivalent, they are merged to one node and one of the redundant drivers is\n");
log("disconnected. A subsequent call to 'clean' will remove the redundant drivers.\n");
log("\n");
log(" -v, -vv\n");
@@ -784,7 +784,7 @@ struct FreducePass : public Pass {
log(" operation. this is mostly used for debugging the freduce command.\n");
log("\n");
log("This pass is undef-aware, i.e. it considers don't-care values for detecting\n");
- log("equivialent nodes.\n");
+ log("equivalent nodes.\n");
log("\n");
log("All selected wires are considered for rewiring. The selected cells cover the\n");
log("circuit that is analyzed.\n");
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 24d7e3a08..682299ef2 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -340,7 +340,7 @@ struct MiterPass : public Pass {
log("\n");
log(" miter -equiv [options] gold_name gate_name miter_name\n");
log("\n");
- log("Creates a miter circuit for equivialence checking. The gold- and gate- modules\n");
+ log("Creates a miter circuit for equivalence checking. The gold- and gate- modules\n");
log("must have the same interfaces. The miter circuit will have all inputs of the\n");
log("two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'\n");
log("output that goes high if an output mismatch between the two source modules is\n");
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 16ec88fe0..ed6526fba 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -1017,7 +1017,7 @@ struct SatPass : public Pass {
log("\n");
log(" -prove-x <signal> <value>\n");
log(" Like -prove, but an undef (x) bit in the lhs matches any value on\n");
- log(" the right hand side. Useful for equivialence checking.\n");
+ log(" the right hand side. Useful for equivalence checking.\n");
log("\n");
log(" -prove-asserts\n");
log(" Prove that all asserts in the design hold.\n");
--
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