From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- passes/sat/eval.cc | 12 ++++++------ passes/sat/expose.cc | 12 ++++++------ passes/sat/freduce.cc | 2 +- passes/sat/miter.cc | 12 ++++++------ passes/sat/sat.cc | 2 +- passes/sat/share.cc | 2 +- 6 files changed, 21 insertions(+), 21 deletions(-) (limited to 'passes/sat') diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 454233267..8a2dd929b 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -306,10 +306,10 @@ struct VlogHammerReporter { for (auto name : split(module_list, ",")) { RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name); - if (design->modules.count(esc_name) == 0) + if (design->modules_.count(esc_name) == 0) log_error("Can't find module %s in current design!\n", name.c_str()); log("Using module %s (%s).\n", esc_name.c_str(), name.c_str()); - modules.push_back(design->modules.at(esc_name)); + modules.push_back(design->modules_.at(esc_name)); module_names.push_back(name); } @@ -416,11 +416,11 @@ struct EvalPass : public Pass { /* this should only be used for regression testing of ConstEval -- see vloghammer */ std::string mod1_name = RTLIL::escape_id(args[++argidx]); std::string mod2_name = RTLIL::escape_id(args[++argidx]); - if (design->modules.count(mod1_name) == 0) + if (design->modules_.count(mod1_name) == 0) log_error("Can't find module `%s'!\n", mod1_name.c_str()); - if (design->modules.count(mod2_name) == 0) + if (design->modules_.count(mod2_name) == 0) log_error("Can't find module `%s'!\n", mod2_name.c_str()); - BruteForceEquivChecker checker(design->modules.at(mod1_name), design->modules.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); + BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); if (checker.errors > 0) log_cmd_error("Modules are not equivialent!\n"); log("Verified %s = %s (using brute-force check on %d cases).\n", @@ -442,7 +442,7 @@ struct EvalPass : public Pass { extra_args(args, argidx, design); RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { if (module) log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n", diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 24b812bb2..f2b89b000 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -50,7 +50,7 @@ static bool consider_cell(RTLIL::Design *design, std::set &dff_cell { if (cell->name[0] == '$' || dff_cells.count(cell->name)) return false; - if (cell->type.at(0) == '\\' && !design->modules.count(cell->type)) + if (cell->type.at(0) == '\\' && !design->modules_.count(cell->type)) return false; return true; } @@ -302,7 +302,7 @@ struct ExposePass : public Pass { RTLIL::Module *first_module = NULL; std::set shared_dff_wires; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; @@ -352,7 +352,7 @@ struct ExposePass : public Pass { { RTLIL::Module *first_module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; @@ -434,7 +434,7 @@ struct ExposePass : public Pass { } } - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; @@ -583,9 +583,9 @@ struct ExposePass : public Pass { RTLIL::Cell *cell = it.second; - if (design->modules.count(cell->type)) + if (design->modules_.count(cell->type)) { - RTLIL::Module *mod = design->modules.at(cell->type); + RTLIL::Module *mod = design->modules_.at(cell->type); for (auto &it : mod->wires_) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index f8d5cf6c4..ad304c723 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -817,7 +817,7 @@ struct FreducePass : public Pass { extra_args(args, argidx, design); int bitcount = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; if (design->selected(module)) bitcount += FreduceWorker(design, module).run(); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 248f934c5..0f00e71a6 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -63,15 +63,15 @@ static void create_miter_equiv(struct Pass *that, std::vector args, std::string gate_name = RTLIL::escape_id(args[argidx++]); std::string miter_name = RTLIL::escape_id(args[argidx++]); - if (design->modules.count(gold_name) == 0) + if (design->modules_.count(gold_name) == 0) log_cmd_error("Can't find gold module %s!\n", gold_name.c_str()); - if (design->modules.count(gate_name) == 0) + if (design->modules_.count(gate_name) == 0) log_cmd_error("Can't find gate module %s!\n", gate_name.c_str()); - if (design->modules.count(miter_name) != 0) + if (design->modules_.count(miter_name) != 0) log_cmd_error("There is already a module %s!\n", gate_name.c_str()); - RTLIL::Module *gold_module = design->modules.at(gold_name); - RTLIL::Module *gate_module = design->modules.at(gate_name); + RTLIL::Module *gold_module = design->modules_.at(gold_name); + RTLIL::Module *gate_module = design->modules_.at(gate_name); for (auto &it : gold_module->wires_) { RTLIL::Wire *w1 = it.second, *w2; @@ -113,7 +113,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; - design->modules[miter_name] = miter_module; + design->modules_[miter_name] = miter_module; RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name); RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 3e1c72224..dce312065 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1141,7 +1141,7 @@ struct SatPass : public Pass { extra_args(args, argidx, design); RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { if (module) log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", diff --git a/passes/sat/share.cc b/passes/sat/share.cc index facacf196..671a631dd 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -961,7 +961,7 @@ struct SharePass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) ShareWorker(config, design, mod_it.second); } -- cgit v1.2.3