From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 15:57:57 +0200 Subject: Manual fixes for new cell connections API --- passes/sat/miter.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes/sat/miter.cc') diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 34355122a..96aa10ba3 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -132,8 +132,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w2->width = w1->width; miter_module->add(w2); - gold_cell->connections()[w1->name] = w2; - gate_cell->connections()[w1->name] = w2; + gold_cell->set(w1->name, w2); + gate_cell->set(w1->name, w2); } if (w1->port_output) @@ -150,8 +150,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w2_gate->width = w1->width; miter_module->add(w2_gate); - gold_cell->connections()[w1->name] = w2_gold; - gate_cell->connections()[w1->name] = w2_gate; + gold_cell->set(w1->name, w2_gold); + gate_cell->set(w1->name, w2_gate); RTLIL::SigSpec this_condition; -- cgit v1.2.3