From 8b508dc90b87c99e13f1fa9f8e79e48c7fa52e90 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 21 Feb 2014 23:34:45 +0100 Subject: Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst --- passes/proc/proc_arst.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 571946573..057378e7c 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -156,8 +156,12 @@ restart_proc_arst: if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) { bool polarity = sync->type == RTLIL::SyncType::STp; if (check_signal(mod, root_sig, sync->signal, polarity)) { - log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); - sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; + if (proc->syncs.size() == 1) { + log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + } else { + log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; + } for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.width); -- cgit v1.2.3 From 1c85584fe5843a43590de3927fe9bde74a04e72e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 19 Jun 2014 12:29:29 +0200 Subject: Do not create $dffsr cells with no-op resets in proc_dff --- passes/proc/proc_dff.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'passes/proc') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 2ec498fb2..c18446512 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -356,6 +356,11 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) rstval.optimize(); sig.optimize(); + if (rstval == sig) { + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + sync_level = NULL; + } + if (sync_always) { if (sync_edge || sync_level || many_async_rules.size() > 0) log_error("Mixed always event with edge and/or level sensitive events!\n"); -- cgit v1.2.3 From 361e0d62ffd90b87c94bfc98ed3cbee1a745cd8f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:41:29 +0200 Subject: Replaced depricated NEW_WIRE macro with module->addWire() calls --- passes/proc/proc_dff.cc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index c18446512..13e4e6606 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -80,7 +80,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; - cell->connections["\\Y"] = sync_low_signals = NEW_WIRE(mod, 1); + cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); mod->add(cell); } @@ -92,7 +92,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; - cell->connections["\\Y"] = NEW_WIRE(mod, 1); + cell->connections["\\Y"] = mod->addWire(NEW_ID); sync_high_signals.append(cell->connections["\\Y"]); mod->add(cell); } @@ -105,7 +105,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; - cell->connections["\\Y"] = sync_high_signals = NEW_WIRE(mod, 1); + cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); mod->add(cell); } @@ -116,7 +116,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.width); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.width); inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = NEW_WIRE(mod, sig_d.width); + inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.width); mod->add(inv_cell); RTLIL::Cell *mux_set_cell = new RTLIL::Cell; @@ -126,7 +126,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = NEW_WIRE(mod, sig_d.width); + mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.width); mod->add(mux_set_cell); RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; @@ -136,7 +136,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = NEW_WIRE(mod, sig_d.width); + mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.width); mod->add(mux_clr_cell); } @@ -168,9 +168,9 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::SigSpec sig_set_inv = NEW_WIRE(mod, sig_in.width); - RTLIL::SigSpec sig_sr_set = NEW_WIRE(mod, sig_in.width); - RTLIL::SigSpec sig_sr_clr = NEW_WIRE(mod, sig_in.width); + RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.width); + RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.width); + RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.width); RTLIL::Cell *inv_set = new RTLIL::Cell; inv_set->name = NEW_ID; @@ -315,7 +315,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) { sync_level = new RTLIL::SyncRule; sync_level->type = RTLIL::SyncType::ST1; - sync_level->signal = NEW_WIRE(mod, 1); + sync_level->signal = mod->addWire(NEW_ID); sync_level->actions.push_back(RTLIL::SigSig(sig, rstval)); free_sync_level = true; -- cgit v1.2.3 From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 19:56:17 +0200 Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width --- passes/proc/proc_arst.cc | 18 +++++------ passes/proc/proc_clean.cc | 8 ++--- passes/proc/proc_dff.cc | 82 +++++++++++++++++++++++------------------------ passes/proc/proc_init.cc | 12 +++---- passes/proc/proc_mux.cc | 44 ++++++++++++------------- 5 files changed, 82 insertions(+), 82 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 057378e7c..a773e5e72 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -28,7 +28,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity) { - if (signal.width != 1) + if (signal.__width != 1) return false; if (signal == ref) return true; @@ -80,13 +80,13 @@ static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::S { for (auto &action : cs->actions) { if (unknown) - rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.width), &rval); + rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.__width), &rval); else rspec.replace(action.first, action.second, &rval); } for (auto sw : cs->switches) { - if (sw->signal.width == 0) { + if (sw->signal.__width == 0) { for (auto cs2 : sw->cases) apply_const(mod, rspec, rval, cs2, const_sig, polarity, unknown); } @@ -164,11 +164,11 @@ restart_proc_arst: } for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; - RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.width); + RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.__width); rspec.expand(), rval.expand(); - for (int i = 0; i < int(rspec.chunks.size()); i++) - if (rspec.chunks[i].wire == NULL) - rval.chunks[i] = rspec.chunks[i]; + for (int i = 0; i < int(rspec.__chunks.size()); i++) + if (rspec.__chunks[i].wire == NULL) + rval.__chunks[i] = rspec.__chunks[i]; rspec.optimize(), rval.optimize(); RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { @@ -252,14 +252,14 @@ struct ProcArstPass : public Pass { if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) for (auto &act : sync->actions) { RTLIL::SigSpec arst_sig, arst_val; - for (auto &chunk : act.first.chunks) + for (auto &chunk : act.first.__chunks) if (chunk.wire && chunk.wire->attributes.count("\\init")) { RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); value.extend(chunk.wire->width, false); arst_sig.append(chunk); arst_val.append(value.extract(chunk.offset, chunk.width)); } - if (arst_sig.width) { + if (arst_sig.__width) { log("Added global reset to process %s: %s <- %s\n", proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val)); arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 83554df90..768660686 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -27,7 +27,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth) { - if (sw->signal.width > 0 && sw->signal.is_fully_const()) + if (sw->signal.__width > 0 && sw->signal.is_fully_const()) { int found_matching_case_idx = -1; for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++) @@ -59,7 +59,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did sw->signal = RTLIL::SigSpec(); } - if (sw->cases.size() == 1 && (sw->signal.width == 0 || sw->cases[0]->compare.empty())) + if (sw->cases.size() == 1 && (sw->signal.__width == 0 || sw->cases[0]->compare.empty())) { did_something = true; for (auto &action : sw->cases[0]->actions) @@ -91,7 +91,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth) { for (size_t i = 0; i < cs->actions.size(); i++) { - if (cs->actions[i].first.width == 0) { + if (cs->actions[i].first.__width == 0) { did_something = true; cs->actions.erase(cs->actions.begin() + (i--)); } @@ -114,7 +114,7 @@ static void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_coun bool did_something = true; for (size_t i = 0; i < proc->syncs.size(); i++) { for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++) - if (proc->syncs[i]->actions[j].first.width == 0) + if (proc->syncs[i]->actions[j].first.__width == 0) proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--)); if (proc->syncs[i]->actions.size() == 0) { delete proc->syncs[i]; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 13e4e6606..d3dff8efc 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -32,7 +32,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) for (auto sync : proc->syncs) for (auto &action : sync->actions) - if (action.first.width > 0) { + if (action.first.__width > 0) { lvalue = action.first; lvalue.sort_and_unify(); break; @@ -44,7 +44,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) this_lvalue.append(action.first); this_lvalue.sort_and_unify(); RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue); - if (common_sig.width > 0) + if (common_sig.__width > 0) lvalue = common_sig; } @@ -54,8 +54,8 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity, std::map> &async_rules, RTLIL::Process *proc) { - RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.width); - RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.width); + RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.__width); + RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.__width); for (auto &it : async_rules) { @@ -72,24 +72,24 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S else log_abort(); - if (sync_low_signals.width > 1) { + if (sync_low_signals.__width > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); mod->add(cell); } - if (sync_low_signals.width > 0) { + if (sync_low_signals.__width > 0) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$not"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = mod->addWire(NEW_ID); @@ -97,12 +97,12 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mod->add(cell); } - if (sync_high_signals.width > 1) { + if (sync_high_signals.__width > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.__width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); @@ -113,30 +113,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S inv_cell->name = NEW_ID; inv_cell->type = "$not"; inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.width); - inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.width); + inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.__width); + inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.__width); inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.width); + inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.__width); mod->add(inv_cell); RTLIL::Cell *mux_set_cell = new RTLIL::Cell; mux_set_cell->name = NEW_ID; mux_set_cell->type = "$mux"; - mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.width); + mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.width); + mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.__width); mod->add(mux_set_cell); RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; mux_clr_cell->name = NEW_ID; mux_clr_cell->type = "$mux"; - mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.width); + mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.width); + mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.__width); mod->add(mux_clr_cell); } @@ -147,7 +147,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -168,16 +168,16 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.width); - RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.width); - RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.width); + RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.__width); + RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.__width); + RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.__width); RTLIL::Cell *inv_set = new RTLIL::Cell; inv_set->name = NEW_ID; inv_set->type = "$not"; inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.width); - inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.width); + inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.__width); + inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.__width); inv_set->connections["\\A"] = sig_set; inv_set->connections["\\Y"] = sig_set_inv; mod->add(inv_set); @@ -185,8 +185,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_set = new RTLIL::Cell; mux_sr_set->name = NEW_ID; mux_sr_set->type = "$mux"; - mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.width); - mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.width); + mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; mux_sr_set->connections["\\Y"] = sig_sr_set; mux_sr_set->connections["\\S"] = set; @@ -195,8 +195,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_clr = new RTLIL::Cell; mux_sr_clr->name = NEW_ID; mux_sr_clr->type = "$mux"; - mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.width); - mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.width); + mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; mux_sr_clr->connections["\\Y"] = sig_sr_clr; mux_sr_clr->connections["\\S"] = set; @@ -206,7 +206,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -233,7 +233,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ cell->attributes = proc->attributes; mod->cells[cell->name] = cell; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); if (arst) { cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1); cell->parameters["\\ARST_VALUE"] = val_rst; @@ -259,14 +259,14 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) RTLIL::SigSpec sig = find_any_lvalue(proc); bool free_sync_level = false; - if (sig.width == 0) + if (sig.__width == 0) break; log("Creating register for signal `%s.%s' using process `%s.%s'.\n", mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str()); - RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); - RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); RTLIL::SyncRule *sync_level = NULL; RTLIL::SyncRule *sync_edge = NULL; RTLIL::SyncRule *sync_always = NULL; @@ -276,16 +276,16 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) for (auto sync : proc->syncs) for (auto &action : sync->actions) { - if (action.first.extract(sig).width == 0) + if (action.first.extract(sig).__width == 0) continue; if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) { if (sync_level != NULL && sync_level != sync) { // log_error("Multiple level sensitive events found for this signal!\n"); many_async_rules[rstval].insert(sync_level); - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); } - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); sig.replace(action.first, action.second, &rstval); sync_level = sync; } @@ -324,15 +324,15 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } - assert(inputs.width == compare.width); + assert(inputs.__width == compare.__width); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$ne"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.width); - cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.__width); + cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.__width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = inputs; cell->connections["\\B"] = compare; @@ -343,7 +343,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } else { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); sync_level = NULL; } } @@ -357,7 +357,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sig.optimize(); if (rstval == sig) { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); sync_level = NULL; } @@ -386,7 +386,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.chunks[0].data, sig, + gen_dff(mod, insig, rstval.__chunks[0].data, sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index fca20fda2..0ef17b22d 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -60,13 +60,13 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.chunks.size(); i++) { - if (lhs.chunks[i].wire == NULL) + for (size_t i = 0; i < lhs.__chunks.size(); i++) { + if (lhs.__chunks[i].wire == NULL) continue; - RTLIL::Wire *wire = lhs.chunks[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks[i].width); - if (value.width != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks[i]), log_signal(value)); + RTLIL::Wire *wire = lhs.__chunks[i].wire; + RTLIL::SigSpec value = rhs.extract(offset, lhs.__chunks[i].width); + if (value.__width != wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.__chunks[i]), log_signal(value)); log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); wire->attributes["\\init"] = value.as_const(); offset += wire->width; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 9b2f83885..2e24e786b 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -28,14 +28,14 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs) { for (auto &action : cs->actions) { - if (action.first.width) + if (action.first.__width) return action.first; } for (auto sw : cs->switches) for (auto cs2 : sw->cases) { RTLIL::SigSpec sig = find_any_lvalue(cs2); - if (sig.width) + if (sig.__width) return sig; } @@ -46,7 +46,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig) { for (auto &action : cs->actions) { RTLIL::SigSpec lvalue = action.first.extract(sig); - if (lvalue.width) + if (lvalue.__width) sig = lvalue; } @@ -72,18 +72,18 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, comp.expand(); // get rid of don't-care bits - assert(sig.width == comp.width); - for (int i = 0; i < comp.width; i++) - if (comp.chunks[i].wire == NULL && comp.chunks[i].data.bits[0] == RTLIL::State::Sa) { + assert(sig.__width == comp.__width); + for (int i = 0; i < comp.__width; i++) + if (comp.__chunks[i].wire == NULL && comp.__chunks[i].data.bits[0] == RTLIL::State::Sa) { sig.remove(i, 1); comp.remove(i--, 1); } - if (comp.width == 0) + if (comp.__width == 0) return RTLIL::SigSpec(); sig.optimize(); comp.optimize(); - if (sig.width == 1 && comp == RTLIL::SigSpec(1,1)) + if (sig.__width == 1 && comp == RTLIL::SigSpec(1,1)) { mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig)); } @@ -101,8 +101,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.__width); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.__width); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); eq_cell->connections["\\A"] = sig; @@ -143,7 +143,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw) { - assert(when_signal.width == else_signal.width); + assert(when_signal.__width == else_signal.__width); std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); @@ -154,14 +154,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, // compare results RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - if (ctrl_sig.width == 0) + if (ctrl_sig.__width == 0) return when_signal; - assert(ctrl_sig.width == 1); + assert(ctrl_sig.__width == 1); // prepare multiplexer output signal RTLIL::Wire *result_wire = new RTLIL::Wire; result_wire->name = sstr.str() + "_Y"; - result_wire->width = when_signal.width; + result_wire->width = when_signal.__width; mod->wires[result_wire->name] = result_wire; // create the multiplexer itself @@ -171,7 +171,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mod->cells[mux_cell->name] = mux_cell; - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.width); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.__width); mux_cell->connections["\\A"] = else_signal; mux_cell->connections["\\B"] = when_signal; mux_cell->connections["\\S"] = ctrl_sig; @@ -184,14 +184,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.width == last_mux_cell->connections["\\A"].width); + assert(when_signal.__width == last_mux_cell->connections["\\A"].__width); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - assert(ctrl_sig.width == 1); + assert(ctrl_sig.__width == 1); last_mux_cell->type = "$pmux"; last_mux_cell->connections["\\S"].append(ctrl_sig); last_mux_cell->connections["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].width; + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].__width; } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -208,7 +208,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs // detect groups of parallel cases std::vector pgroups(sw->cases.size()); if (!sw->get_bool_attribute("\\parallel_case")) { - BitPatternPool pool(sw->signal.width); + BitPatternPool pool(sw->signal.__width); bool extra_group_for_next_case = false; for (size_t i = 0; i < sw->cases.size(); i++) { RTLIL::CaseRule *cs2 = sw->cases[i]; @@ -224,7 +224,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs if (cs2->compare.empty()) pgroups[i] = pgroups[i-1]+1; if (pgroups[i] != pgroups[i-1]) - pool = BitPatternPool(sw->signal.width); + pool = BitPatternPool(sw->signal.__width); } for (auto pat : cs2->compare) if (!pat.is_fully_const()) @@ -258,7 +258,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) { RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case); - if (sig.width == 0) + if (sig.__width == 0) break; if (first) { @@ -270,7 +270,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); - RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.width)); + RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.__width)); mod->connections.push_back(RTLIL::SigSig(sig, value)); } } -- cgit v1.2.3 From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- passes/proc/proc_arst.cc | 18 +++++------ passes/proc/proc_clean.cc | 8 ++--- passes/proc/proc_dff.cc | 82 +++++++++++++++++++++++------------------------ passes/proc/proc_init.cc | 12 +++---- passes/proc/proc_mux.cc | 44 ++++++++++++------------- 5 files changed, 82 insertions(+), 82 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index a773e5e72..b5763508a 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -28,7 +28,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity) { - if (signal.__width != 1) + if (signal.size() != 1) return false; if (signal == ref) return true; @@ -80,13 +80,13 @@ static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::S { for (auto &action : cs->actions) { if (unknown) - rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.__width), &rval); + rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.size()), &rval); else rspec.replace(action.first, action.second, &rval); } for (auto sw : cs->switches) { - if (sw->signal.__width == 0) { + if (sw->signal.size() == 0) { for (auto cs2 : sw->cases) apply_const(mod, rspec, rval, cs2, const_sig, polarity, unknown); } @@ -164,11 +164,11 @@ restart_proc_arst: } for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; - RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.__width); + RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); rspec.expand(), rval.expand(); - for (int i = 0; i < int(rspec.__chunks.size()); i++) - if (rspec.__chunks[i].wire == NULL) - rval.__chunks[i] = rspec.__chunks[i]; + for (int i = 0; i < int(rspec.chunks().size()); i++) + if (rspec.chunks()[i].wire == NULL) + rval.chunks()[i] = rspec.chunks()[i]; rspec.optimize(), rval.optimize(); RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { @@ -252,14 +252,14 @@ struct ProcArstPass : public Pass { if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) for (auto &act : sync->actions) { RTLIL::SigSpec arst_sig, arst_val; - for (auto &chunk : act.first.__chunks) + for (auto &chunk : act.first.chunks()) if (chunk.wire && chunk.wire->attributes.count("\\init")) { RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); value.extend(chunk.wire->width, false); arst_sig.append(chunk); arst_val.append(value.extract(chunk.offset, chunk.width)); } - if (arst_sig.__width) { + if (arst_sig.size()) { log("Added global reset to process %s: %s <- %s\n", proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val)); arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 768660686..682515c5e 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -27,7 +27,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth) { - if (sw->signal.__width > 0 && sw->signal.is_fully_const()) + if (sw->signal.size() > 0 && sw->signal.is_fully_const()) { int found_matching_case_idx = -1; for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++) @@ -59,7 +59,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did sw->signal = RTLIL::SigSpec(); } - if (sw->cases.size() == 1 && (sw->signal.__width == 0 || sw->cases[0]->compare.empty())) + if (sw->cases.size() == 1 && (sw->signal.size() == 0 || sw->cases[0]->compare.empty())) { did_something = true; for (auto &action : sw->cases[0]->actions) @@ -91,7 +91,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth) { for (size_t i = 0; i < cs->actions.size(); i++) { - if (cs->actions[i].first.__width == 0) { + if (cs->actions[i].first.size() == 0) { did_something = true; cs->actions.erase(cs->actions.begin() + (i--)); } @@ -114,7 +114,7 @@ static void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_coun bool did_something = true; for (size_t i = 0; i < proc->syncs.size(); i++) { for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++) - if (proc->syncs[i]->actions[j].first.__width == 0) + if (proc->syncs[i]->actions[j].first.size() == 0) proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--)); if (proc->syncs[i]->actions.size() == 0) { delete proc->syncs[i]; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index d3dff8efc..8e5fbe8f4 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -32,7 +32,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) for (auto sync : proc->syncs) for (auto &action : sync->actions) - if (action.first.__width > 0) { + if (action.first.size() > 0) { lvalue = action.first; lvalue.sort_and_unify(); break; @@ -44,7 +44,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) this_lvalue.append(action.first); this_lvalue.sort_and_unify(); RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue); - if (common_sig.__width > 0) + if (common_sig.size() > 0) lvalue = common_sig; } @@ -54,8 +54,8 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity, std::map> &async_rules, RTLIL::Process *proc) { - RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.__width); - RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.__width); + RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size()); + RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size()); for (auto &it : async_rules) { @@ -72,24 +72,24 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S else log_abort(); - if (sync_low_signals.__width > 1) { + if (sync_low_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); mod->add(cell); } - if (sync_low_signals.__width > 0) { + if (sync_low_signals.size() > 0) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$not"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = mod->addWire(NEW_ID); @@ -97,12 +97,12 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mod->add(cell); } - if (sync_high_signals.__width > 1) { + if (sync_high_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); @@ -113,30 +113,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S inv_cell->name = NEW_ID; inv_cell->type = "$not"; inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.__width); - inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.__width); + inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); + inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.__width); + inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); mod->add(inv_cell); RTLIL::Cell *mux_set_cell = new RTLIL::Cell; mux_set_cell->name = NEW_ID; mux_set_cell->type = "$mux"; - mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.__width); + mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); mod->add(mux_set_cell); RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; mux_clr_cell->name = NEW_ID; mux_clr_cell->type = "$mux"; - mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.__width); + mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); mod->add(mux_clr_cell); } @@ -147,7 +147,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -168,16 +168,16 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.__width); - RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.__width); - RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.__width); + RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size()); + RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); + RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size()); RTLIL::Cell *inv_set = new RTLIL::Cell; inv_set->name = NEW_ID; inv_set->type = "$not"; inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.__width); - inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.__width); + inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); + inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->connections["\\A"] = sig_set; inv_set->connections["\\Y"] = sig_set_inv; mod->add(inv_set); @@ -185,8 +185,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_set = new RTLIL::Cell; mux_sr_set->name = NEW_ID; mux_sr_set->type = "$mux"; - mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); - mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); + mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); + mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; mux_sr_set->connections["\\Y"] = sig_sr_set; mux_sr_set->connections["\\S"] = set; @@ -195,8 +195,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_clr = new RTLIL::Cell; mux_sr_clr->name = NEW_ID; mux_sr_clr->type = "$mux"; - mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); - mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); + mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); + mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; mux_sr_clr->connections["\\Y"] = sig_sr_clr; mux_sr_clr->connections["\\S"] = set; @@ -206,7 +206,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -233,7 +233,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ cell->attributes = proc->attributes; mod->cells[cell->name] = cell; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); if (arst) { cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1); cell->parameters["\\ARST_VALUE"] = val_rst; @@ -259,14 +259,14 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) RTLIL::SigSpec sig = find_any_lvalue(proc); bool free_sync_level = false; - if (sig.__width == 0) + if (sig.size() == 0) break; log("Creating register for signal `%s.%s' using process `%s.%s'.\n", mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str()); - RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); - RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); + RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); RTLIL::SyncRule *sync_level = NULL; RTLIL::SyncRule *sync_edge = NULL; RTLIL::SyncRule *sync_always = NULL; @@ -276,16 +276,16 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) for (auto sync : proc->syncs) for (auto &action : sync->actions) { - if (action.first.extract(sig).__width == 0) + if (action.first.extract(sig).size() == 0) continue; if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) { if (sync_level != NULL && sync_level != sync) { // log_error("Multiple level sensitive events found for this signal!\n"); many_async_rules[rstval].insert(sync_level); - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); } - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sig.replace(action.first, action.second, &rstval); sync_level = sync; } @@ -324,15 +324,15 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } - assert(inputs.__width == compare.__width); + assert(inputs.size() == compare.size()); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$ne"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.__width); - cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); + cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = inputs; cell->connections["\\B"] = compare; @@ -343,7 +343,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } else { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } } @@ -357,7 +357,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sig.optimize(); if (rstval == sig) { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } @@ -386,7 +386,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.__chunks[0].data, sig, + gen_dff(mod, insig, rstval.chunks()[0].data, sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 0ef17b22d..ba1fb5ab9 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -60,13 +60,13 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.__chunks.size(); i++) { - if (lhs.__chunks[i].wire == NULL) + for (size_t i = 0; i < lhs.chunks().size(); i++) { + if (lhs.chunks()[i].wire == NULL) continue; - RTLIL::Wire *wire = lhs.__chunks[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.__chunks[i].width); - if (value.__width != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.__chunks[i]), log_signal(value)); + RTLIL::Wire *wire = lhs.chunks()[i].wire; + RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width); + if (value.size() != wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value)); log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); wire->attributes["\\init"] = value.as_const(); offset += wire->width; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2e24e786b..cd459d949 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -28,14 +28,14 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs) { for (auto &action : cs->actions) { - if (action.first.__width) + if (action.first.size()) return action.first; } for (auto sw : cs->switches) for (auto cs2 : sw->cases) { RTLIL::SigSpec sig = find_any_lvalue(cs2); - if (sig.__width) + if (sig.size()) return sig; } @@ -46,7 +46,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig) { for (auto &action : cs->actions) { RTLIL::SigSpec lvalue = action.first.extract(sig); - if (lvalue.__width) + if (lvalue.size()) sig = lvalue; } @@ -72,18 +72,18 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, comp.expand(); // get rid of don't-care bits - assert(sig.__width == comp.__width); - for (int i = 0; i < comp.__width; i++) - if (comp.__chunks[i].wire == NULL && comp.__chunks[i].data.bits[0] == RTLIL::State::Sa) { + assert(sig.size() == comp.size()); + for (int i = 0; i < comp.size(); i++) + if (comp.chunks()[i].wire == NULL && comp.chunks()[i].data.bits[0] == RTLIL::State::Sa) { sig.remove(i, 1); comp.remove(i--, 1); } - if (comp.__width == 0) + if (comp.size() == 0) return RTLIL::SigSpec(); sig.optimize(); comp.optimize(); - if (sig.__width == 1 && comp == RTLIL::SigSpec(1,1)) + if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig)); } @@ -101,8 +101,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.__width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.__width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size()); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); eq_cell->connections["\\A"] = sig; @@ -143,7 +143,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw) { - assert(when_signal.__width == else_signal.__width); + assert(when_signal.size() == else_signal.size()); std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); @@ -154,14 +154,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, // compare results RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - if (ctrl_sig.__width == 0) + if (ctrl_sig.size() == 0) return when_signal; - assert(ctrl_sig.__width == 1); + assert(ctrl_sig.size() == 1); // prepare multiplexer output signal RTLIL::Wire *result_wire = new RTLIL::Wire; result_wire->name = sstr.str() + "_Y"; - result_wire->width = when_signal.__width; + result_wire->width = when_signal.size(); mod->wires[result_wire->name] = result_wire; // create the multiplexer itself @@ -171,7 +171,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mod->cells[mux_cell->name] = mux_cell; - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.__width); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); mux_cell->connections["\\A"] = else_signal; mux_cell->connections["\\B"] = when_signal; mux_cell->connections["\\S"] = ctrl_sig; @@ -184,14 +184,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.__width == last_mux_cell->connections["\\A"].__width); + assert(when_signal.size() == last_mux_cell->connections["\\A"].size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - assert(ctrl_sig.__width == 1); + assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; last_mux_cell->connections["\\S"].append(ctrl_sig); last_mux_cell->connections["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].__width; + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -208,7 +208,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs // detect groups of parallel cases std::vector pgroups(sw->cases.size()); if (!sw->get_bool_attribute("\\parallel_case")) { - BitPatternPool pool(sw->signal.__width); + BitPatternPool pool(sw->signal.size()); bool extra_group_for_next_case = false; for (size_t i = 0; i < sw->cases.size(); i++) { RTLIL::CaseRule *cs2 = sw->cases[i]; @@ -224,7 +224,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs if (cs2->compare.empty()) pgroups[i] = pgroups[i-1]+1; if (pgroups[i] != pgroups[i-1]) - pool = BitPatternPool(sw->signal.__width); + pool = BitPatternPool(sw->signal.size()); } for (auto pat : cs2->compare) if (!pat.is_fully_const()) @@ -258,7 +258,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) { RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case); - if (sig.__width == 0) + if (sig.size() == 0) break; if (first) { @@ -270,7 +270,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); - RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.__width)); + RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size())); mod->connections.push_back(RTLIL::SigSig(sig, value)); } } -- cgit v1.2.3 From 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:58:44 +0200 Subject: SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() --- passes/proc/proc_arst.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index b5763508a..6cb560f5c 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -168,7 +168,7 @@ restart_proc_arst: rspec.expand(), rval.expand(); for (int i = 0; i < int(rspec.chunks().size()); i++) if (rspec.chunks()[i].wire == NULL) - rval.chunks()[i] = rspec.chunks()[i]; + rval.chunks_rw()[i] = rspec.chunks()[i]; rspec.optimize(), rval.optimize(); RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { -- cgit v1.2.3 From 65a939cb2767623b95adcd2ec5e783b828c1f9eb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 22:54:39 +0200 Subject: Fixed memory corruption with new SigSpec API in proc_mux --- passes/proc/proc_mux.cc | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index cd459d949..50ba8fa1e 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -68,20 +68,16 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, for (auto comp : compare) { RTLIL::SigSpec sig = signal; - sig.expand(); - comp.expand(); // get rid of don't-care bits assert(sig.size() == comp.size()); for (int i = 0; i < comp.size(); i++) - if (comp.chunks()[i].wire == NULL && comp.chunks()[i].data.bits[0] == RTLIL::State::Sa) { - sig.remove(i, 1); - comp.remove(i--, 1); + if (comp[i] == RTLIL::State::Sa) { + sig.remove(i); + comp.remove(i--); } if (comp.size() == 0) return RTLIL::SigSpec(); - sig.optimize(); - comp.optimize(); if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { -- cgit v1.2.3 From a8d3a68971ccc4e47c54a906aae374a9a54b1415 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 08:40:31 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 --- passes/proc/proc_mux.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 50ba8fa1e..0fe765732 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { - mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig)); + mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++), sig)); } else { @@ -103,7 +103,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->connections["\\A"] = sig; eq_cell->connections["\\B"] = comp; - eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++); + eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++); } } -- cgit v1.2.3 From ec923652e2eb721aa16657e54a67666f855c3d65 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 09:48:26 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 --- passes/proc/proc_mux.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 0fe765732..804c51fd3 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { - mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++), sig)); + mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); } else { @@ -103,7 +103,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->connections["\\A"] = sig; eq_cell->connections["\\B"] = comp; - eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++); + eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++); } } -- cgit v1.2.3 From 4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 15:36:09 +0200 Subject: Fixed all users of SigSpec::chunks_rw() and removed it --- passes/proc/proc_arst.cc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 6cb560f5c..145abfa43 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -165,11 +165,9 @@ restart_proc_arst: for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); - rspec.expand(), rval.expand(); - for (int i = 0; i < int(rspec.chunks().size()); i++) - if (rspec.chunks()[i].wire == NULL) - rval.chunks_rw()[i] = rspec.chunks()[i]; - rspec.optimize(), rval.optimize(); + for (int i = 0; i < SIZE(rspec); i++) + if (rspec[i].wire == NULL) + rval[i] = rspec[i]; RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { last_rval = rval; -- cgit v1.2.3 From c094c53de83707a5bf1b268640283f1dde235873 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:32:28 +0200 Subject: Removed RTLIL::SigSpec::optimize() --- passes/proc/proc_dff.cc | 4 ---- passes/proc/proc_init.cc | 2 -- 2 files changed, 6 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 8e5fbe8f4..a8aba903a 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -352,10 +352,6 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) ce.assign_map.apply(rstval); ce.assign_map.apply(sig); - insig.optimize(); - rstval.optimize(); - sig.optimize(); - if (rstval == sig) { rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index ba1fb5ab9..4c9b6bcd2 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -28,7 +28,6 @@ static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule) assert(rule.compare.size() == 0); while (1) { - sig.optimize(); RTLIL::SigSpec tmp = sig; for (auto &it : rule.actions) tmp.replace(it.first, it.second); @@ -53,7 +52,6 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) RTLIL::SigSpec lhs = action.first; RTLIL::SigSpec rhs = action.second; - lhs.optimize(); proc_get_const(rhs, proc->root_case); if (!rhs.is_fully_const()) -- cgit v1.2.3 From 6aa792c864444324a1b140c2b63bd860f0cc3914 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 22:47:57 +0200 Subject: Replaced more old SigChunk programming patterns --- passes/proc/proc_dff.cc | 2 +- passes/proc/proc_init.cc | 19 +++++++++---------- 2 files changed, 10 insertions(+), 11 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index a8aba903a..5982fd8e4 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -382,7 +382,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.chunks()[0].data, sig, + gen_dff(mod, insig, rstval.as_const(), sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 4c9b6bcd2..5976c2162 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -58,16 +58,15 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.chunks().size(); i++) { - if (lhs.chunks()[i].wire == NULL) - continue; - RTLIL::Wire *wire = lhs.chunks()[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width); - if (value.size() != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value)); - log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); - wire->attributes["\\init"] = value.as_const(); - offset += wire->width; + for (auto &lhs_c : lhs.chunks()) { + if (lhs_c.wire != NULL) { + RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width); + if (value.size() != lhs_c.wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value)); + log(" Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value)); + lhs_c.wire->attributes["\\init"] = value.as_const(); + } + offset += lhs_c.width; } } } -- cgit v1.2.3 From 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 15:05:18 +0200 Subject: Use only module->addCell() and module->remove() to create and delete cells --- passes/proc/proc_dff.cc | 65 ++++++++++--------------------------------------- passes/proc/proc_mux.cc | 17 +++---------- 2 files changed, 16 insertions(+), 66 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 5982fd8e4..876adb0db 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -73,79 +73,59 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S log_abort(); if (sync_low_signals.size() > 1) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$reduce_or"; + RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); - mod->add(cell); } if (sync_low_signals.size() > 0) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$not"; + RTLIL::Cell *cell = mod->addCell(NEW_ID, "$not"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = mod->addWire(NEW_ID); sync_high_signals.append(cell->connections["\\Y"]); - mod->add(cell); } if (sync_high_signals.size() > 1) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$reduce_or"; + RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); - mod->add(cell); } - RTLIL::Cell *inv_cell = new RTLIL::Cell; - inv_cell->name = NEW_ID; - inv_cell->type = "$not"; + RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->connections["\\A"] = sync_value; inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); - mod->add(inv_cell); - RTLIL::Cell *mux_set_cell = new RTLIL::Cell; - mux_set_cell->name = NEW_ID; - mux_set_cell->type = "$mux"; + RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); - mod->add(mux_set_cell); - RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; - mux_clr_cell->name = NEW_ID; - mux_clr_cell->type = "$mux"; + RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); - mod->add(mux_clr_cell); } std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = sstr.str(); - cell->type = "$dffsr"; + RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); @@ -156,7 +136,6 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->connections["\\CLK"] = clk; cell->connections["\\SET"] = sig_sr_set; cell->connections["\\CLR"] = sig_sr_clr; - mod->add(cell); log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -172,39 +151,28 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size()); - RTLIL::Cell *inv_set = new RTLIL::Cell; - inv_set->name = NEW_ID; - inv_set->type = "$not"; + RTLIL::Cell *inv_set = mod->addCell(NEW_ID, "$not"); inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->connections["\\A"] = sig_set; inv_set->connections["\\Y"] = sig_set_inv; - mod->add(inv_set); - RTLIL::Cell *mux_sr_set = new RTLIL::Cell; - mux_sr_set->name = NEW_ID; - mux_sr_set->type = "$mux"; + RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; mux_sr_set->connections["\\Y"] = sig_sr_set; mux_sr_set->connections["\\S"] = set; - mod->add(mux_sr_set); - RTLIL::Cell *mux_sr_clr = new RTLIL::Cell; - mux_sr_clr->name = NEW_ID; - mux_sr_clr->type = "$mux"; + RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; mux_sr_clr->connections["\\Y"] = sig_sr_clr; mux_sr_clr->connections["\\S"] = set; - mod->add(mux_sr_clr); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = sstr.str(); - cell->type = "$dffsr"; + RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); @@ -215,7 +183,6 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->connections["\\CLK"] = clk; cell->connections["\\SET"] = sig_sr_set; cell->connections["\\CLR"] = sig_sr_clr; - mod->add(cell); log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -227,11 +194,8 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = sstr.str(); - cell->type = arst ? "$adff" : "$dff"; + RTLIL::Cell *cell = mod->addCell(sstr.str(), arst ? "$adff" : "$dff"); cell->attributes = proc->attributes; - mod->cells[cell->name] = cell; cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); if (arst) { @@ -326,9 +290,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } assert(inputs.size() == compare.size()); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$ne"; + RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); @@ -337,7 +299,6 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) cell->connections["\\A"] = inputs; cell->connections["\\B"] = compare; cell->connections["\\Y"] = sync_level->signal; - mod->add(cell); many_async_rules.clear(); } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 804c51fd3..5bb1ab948 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -86,13 +86,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, else { // create compare cell - RTLIL::Cell *eq_cell = new RTLIL::Cell; - std::stringstream sstr2; - sstr2 << sstr.str() << "_CMP" << cmp_wire->width; - eq_cell->name = sstr2.str(); - eq_cell->type = "$eq"; + RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), "$eq"); eq_cell->attributes = sw->attributes; - mod->cells[eq_cell->name] = eq_cell; eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); @@ -120,11 +115,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mod->wires[ctrl_wire->name] = ctrl_wire; // reduce cmp vector to one logic signal - RTLIL::Cell *any_cell = new RTLIL::Cell; - any_cell->name = sstr.str() + "_ANY"; - any_cell->type = "$reduce_or"; + RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or"); any_cell->attributes = sw->attributes; - mod->cells[any_cell->name] = any_cell; any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); @@ -161,11 +153,8 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mod->wires[result_wire->name] = result_wire; // create the multiplexer itself - RTLIL::Cell *mux_cell = new RTLIL::Cell; - mux_cell->name = sstr.str(); - mux_cell->type = "$mux"; + RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux"); mux_cell->attributes = sw->attributes; - mod->cells[mux_cell->name] = mux_cell; mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); mux_cell->connections["\\A"] = else_signal; -- cgit v1.2.3 From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- passes/proc/proc_arst.cc | 44 +++++++++++------------ passes/proc/proc_dff.cc | 90 ++++++++++++++++++++++++------------------------ passes/proc/proc_mux.cc | 30 ++++++++-------- 3 files changed, 82 insertions(+), 82 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 145abfa43..ce3133601 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -35,40 +35,40 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp for (auto &cell_it : mod->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$reduce_or" && cell->connections["\\Y"] == signal) - return check_signal(mod, cell->connections["\\A"], ref, polarity); - if (cell->type == "$reduce_bool" && cell->connections["\\Y"] == signal) - return check_signal(mod, cell->connections["\\A"], ref, polarity); - if (cell->type == "$logic_not" && cell->connections["\\Y"] == signal) { + if (cell->type == "$reduce_or" && cell->connections_["\\Y"] == signal) + return check_signal(mod, cell->connections_["\\A"], ref, polarity); + if (cell->type == "$reduce_bool" && cell->connections_["\\Y"] == signal) + return check_signal(mod, cell->connections_["\\A"], ref, polarity); + if (cell->type == "$logic_not" && cell->connections_["\\Y"] == signal) { polarity = !polarity; - return check_signal(mod, cell->connections["\\A"], ref, polarity); + return check_signal(mod, cell->connections_["\\A"], ref, polarity); } - if (cell->type == "$not" && cell->connections["\\Y"] == signal) { + if (cell->type == "$not" && cell->connections_["\\Y"] == signal) { polarity = !polarity; - return check_signal(mod, cell->connections["\\A"], ref, polarity); + return check_signal(mod, cell->connections_["\\A"], ref, polarity); } - if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections["\\Y"] == signal) { - if (cell->connections["\\A"].is_fully_const()) { - if (!cell->connections["\\A"].as_bool()) + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections_["\\Y"] == signal) { + if (cell->connections_["\\A"].is_fully_const()) { + if (!cell->connections_["\\A"].as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections["\\B"], ref, polarity); + return check_signal(mod, cell->connections_["\\B"], ref, polarity); } - if (cell->connections["\\B"].is_fully_const()) { - if (!cell->connections["\\B"].as_bool()) + if (cell->connections_["\\B"].is_fully_const()) { + if (!cell->connections_["\\B"].as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections["\\A"], ref, polarity); + return check_signal(mod, cell->connections_["\\A"], ref, polarity); } } - if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections["\\Y"] == signal) { - if (cell->connections["\\A"].is_fully_const()) { - if (cell->connections["\\A"].as_bool()) + if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections_["\\Y"] == signal) { + if (cell->connections_["\\A"].is_fully_const()) { + if (cell->connections_["\\A"].as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections["\\B"], ref, polarity); + return check_signal(mod, cell->connections_["\\B"], ref, polarity); } - if (cell->connections["\\B"].is_fully_const()) { - if (cell->connections["\\B"].as_bool()) + if (cell->connections_["\\B"].is_fully_const()) { + if (cell->connections_["\\B"].as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections["\\A"], ref, polarity); + return check_signal(mod, cell->connections_["\\A"], ref, polarity); } } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 876adb0db..9d2c897ee 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -77,8 +77,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections["\\A"] = sync_low_signals; - cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); + cell->connections_["\\A"] = sync_low_signals; + cell->connections_["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); } if (sync_low_signals.size() > 0) { @@ -86,9 +86,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections["\\A"] = sync_low_signals; - cell->connections["\\Y"] = mod->addWire(NEW_ID); - sync_high_signals.append(cell->connections["\\Y"]); + cell->connections_["\\A"] = sync_low_signals; + cell->connections_["\\Y"] = mod->addWire(NEW_ID); + sync_high_signals.append(cell->connections_["\\Y"]); } if (sync_high_signals.size() > 1) { @@ -96,30 +96,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections["\\A"] = sync_high_signals; - cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); + cell->connections_["\\A"] = sync_high_signals; + cell->connections_["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); } RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); - inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); + inv_cell->connections_["\\A"] = sync_value; + inv_cell->connections_["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_set_cell->connections["\\A"] = sig_sr_set; - mux_set_cell->connections["\\B"] = sync_value; - mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); + mux_set_cell->connections_["\\A"] = sig_sr_set; + mux_set_cell->connections_["\\B"] = sync_value; + mux_set_cell->connections_["\\S"] = sync_high_signals; + mux_set_cell->connections_["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_clr_cell->connections["\\A"] = sig_sr_clr; - mux_clr_cell->connections["\\B"] = sync_value_inv; - mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); + mux_clr_cell->connections_["\\A"] = sig_sr_clr; + mux_clr_cell->connections_["\\B"] = sync_value_inv; + mux_clr_cell->connections_["\\S"] = sync_high_signals; + mux_clr_cell->connections_["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); } std::stringstream sstr; @@ -131,11 +131,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; - cell->connections["\\CLK"] = clk; - cell->connections["\\SET"] = sig_sr_set; - cell->connections["\\CLR"] = sig_sr_clr; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; + cell->connections_["\\CLK"] = clk; + cell->connections_["\\SET"] = sig_sr_set; + cell->connections_["\\CLR"] = sig_sr_clr; log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -155,22 +155,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); - inv_set->connections["\\A"] = sig_set; - inv_set->connections["\\Y"] = sig_set_inv; + inv_set->connections_["\\A"] = sig_set; + inv_set->connections_["\\Y"] = sig_set_inv; RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; - mux_sr_set->connections["\\Y"] = sig_sr_set; - mux_sr_set->connections["\\S"] = set; + mux_sr_set->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); + mux_sr_set->connections_[set_polarity ? "\\B" : "\\A"] = sig_set; + mux_sr_set->connections_["\\Y"] = sig_sr_set; + mux_sr_set->connections_["\\S"] = set; RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; - mux_sr_clr->connections["\\Y"] = sig_sr_clr; - mux_sr_clr->connections["\\S"] = set; + mux_sr_clr->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); + mux_sr_clr->connections_[set_polarity ? "\\B" : "\\A"] = sig_set_inv; + mux_sr_clr->connections_["\\Y"] = sig_sr_clr; + mux_sr_clr->connections_["\\S"] = set; RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; @@ -178,11 +178,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->connections["\\D"] = sig_in; - cell->connections["\\Q"] = sig_out; - cell->connections["\\CLK"] = clk; - cell->connections["\\SET"] = sig_sr_set; - cell->connections["\\CLR"] = sig_sr_clr; + cell->connections_["\\D"] = sig_in; + cell->connections_["\\Q"] = sig_out; + cell->connections_["\\CLK"] = clk; + cell->connections_["\\SET"] = sig_sr_set; + cell->connections_["\\CLR"] = sig_sr_clr; log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -204,11 +204,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ } cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); - cell->connections["\\D"] = sig_in; - cell->connections["\\Q"] = sig_out; + cell->connections_["\\D"] = sig_in; + cell->connections_["\\Q"] = sig_out; if (arst) - cell->connections["\\ARST"] = *arst; - cell->connections["\\CLK"] = clk; + cell->connections_["\\ARST"] = *arst; + cell->connections_["\\CLK"] = clk; log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); if (arst) @@ -296,9 +296,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections["\\A"] = inputs; - cell->connections["\\B"] = compare; - cell->connections["\\Y"] = sync_level->signal; + cell->connections_["\\A"] = inputs; + cell->connections_["\\B"] = compare; + cell->connections_["\\Y"] = sync_level->signal; many_async_rules.clear(); } @@ -322,7 +322,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) if (sync_edge || sync_level || many_async_rules.size() > 0) log_error("Mixed always event with edge and/or level sensitive events!\n"); log(" created direct connection (no actual register cell created).\n"); - mod->connections.push_back(RTLIL::SigSig(sig, insig)); + mod->connections_.push_back(RTLIL::SigSig(sig, insig)); continue; } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 5bb1ab948..2cde749a5 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { - mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); + mod->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); } else { @@ -96,9 +96,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - eq_cell->connections["\\A"] = sig; - eq_cell->connections["\\B"] = comp; - eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++); + eq_cell->connections_["\\A"] = sig; + eq_cell->connections_["\\B"] = comp; + eq_cell->connections_["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++); } } @@ -122,8 +122,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - any_cell->connections["\\A"] = cmp_wire; - any_cell->connections["\\Y"] = RTLIL::SigSpec(ctrl_wire); + any_cell->connections_["\\A"] = cmp_wire; + any_cell->connections_["\\Y"] = RTLIL::SigSpec(ctrl_wire); } return RTLIL::SigSpec(ctrl_wire); @@ -157,10 +157,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); - mux_cell->connections["\\A"] = else_signal; - mux_cell->connections["\\B"] = when_signal; - mux_cell->connections["\\S"] = ctrl_sig; - mux_cell->connections["\\Y"] = RTLIL::SigSpec(result_wire); + mux_cell->connections_["\\A"] = else_signal; + mux_cell->connections_["\\B"] = when_signal; + mux_cell->connections_["\\S"] = ctrl_sig; + mux_cell->connections_["\\Y"] = RTLIL::SigSpec(result_wire); last_mux_cell = mux_cell; return RTLIL::SigSpec(result_wire); @@ -169,14 +169,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.size() == last_mux_cell->connections["\\A"].size()); + assert(when_signal.size() == last_mux_cell->connections_["\\A"].size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - last_mux_cell->connections["\\S"].append(ctrl_sig); - last_mux_cell->connections["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].size(); + last_mux_cell->connections_["\\S"].append(ctrl_sig); + last_mux_cell->connections_["\\B"].append(when_signal); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections_["\\S"].size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -256,7 +256,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size())); - mod->connections.push_back(RTLIL::SigSig(sig, value)); + mod->connections_.push_back(RTLIL::SigSig(sig, value)); } } -- cgit v1.2.3 From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- passes/proc/proc_arst.cc | 44 +++++++++++------------ passes/proc/proc_dff.cc | 90 ++++++++++++++++++++++++------------------------ passes/proc/proc_mux.cc | 30 ++++++++-------- 3 files changed, 82 insertions(+), 82 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index ce3133601..114f2567e 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -35,40 +35,40 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp for (auto &cell_it : mod->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$reduce_or" && cell->connections_["\\Y"] == signal) - return check_signal(mod, cell->connections_["\\A"], ref, polarity); - if (cell->type == "$reduce_bool" && cell->connections_["\\Y"] == signal) - return check_signal(mod, cell->connections_["\\A"], ref, polarity); - if (cell->type == "$logic_not" && cell->connections_["\\Y"] == signal) { + if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) + return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal) + return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$logic_not" && cell->get("\\Y") == signal) { polarity = !polarity; - return check_signal(mod, cell->connections_["\\A"], ref, polarity); + return check_signal(mod, cell->get("\\A"), ref, polarity); } - if (cell->type == "$not" && cell->connections_["\\Y"] == signal) { + if (cell->type == "$not" && cell->get("\\Y") == signal) { polarity = !polarity; - return check_signal(mod, cell->connections_["\\A"], ref, polarity); + return check_signal(mod, cell->get("\\A"), ref, polarity); } - if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections_["\\Y"] == signal) { - if (cell->connections_["\\A"].is_fully_const()) { - if (!cell->connections_["\\A"].as_bool()) + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) { + if (cell->get("\\A").is_fully_const()) { + if (!cell->get("\\A").as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections_["\\B"], ref, polarity); + return check_signal(mod, cell->get("\\B"), ref, polarity); } - if (cell->connections_["\\B"].is_fully_const()) { - if (!cell->connections_["\\B"].as_bool()) + if (cell->get("\\B").is_fully_const()) { + if (!cell->get("\\B").as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections_["\\A"], ref, polarity); + return check_signal(mod, cell->get("\\A"), ref, polarity); } } - if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections_["\\Y"] == signal) { - if (cell->connections_["\\A"].is_fully_const()) { - if (cell->connections_["\\A"].as_bool()) + if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) { + if (cell->get("\\A").is_fully_const()) { + if (cell->get("\\A").as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections_["\\B"], ref, polarity); + return check_signal(mod, cell->get("\\B"), ref, polarity); } - if (cell->connections_["\\B"].is_fully_const()) { - if (cell->connections_["\\B"].as_bool()) + if (cell->get("\\B").is_fully_const()) { + if (cell->get("\\B").as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections_["\\A"], ref, polarity); + return check_signal(mod, cell->get("\\A"), ref, polarity); } } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 9d2c897ee..2e2d4701f 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -77,8 +77,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections_["\\A"] = sync_low_signals; - cell->connections_["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); + cell->set("\\A", sync_low_signals); + cell->set("\\Y", sync_low_signals = mod->addWire(NEW_ID)); } if (sync_low_signals.size() > 0) { @@ -86,9 +86,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections_["\\A"] = sync_low_signals; - cell->connections_["\\Y"] = mod->addWire(NEW_ID); - sync_high_signals.append(cell->connections_["\\Y"]); + cell->set("\\A", sync_low_signals); + cell->set("\\Y", mod->addWire(NEW_ID)); + sync_high_signals.append(cell->get("\\Y")); } if (sync_high_signals.size() > 1) { @@ -96,30 +96,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections_["\\A"] = sync_high_signals; - cell->connections_["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); + cell->set("\\A", sync_high_signals); + cell->set("\\Y", sync_high_signals = mod->addWire(NEW_ID)); } RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); - inv_cell->connections_["\\A"] = sync_value; - inv_cell->connections_["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); + inv_cell->set("\\A", sync_value); + inv_cell->set("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_set_cell->connections_["\\A"] = sig_sr_set; - mux_set_cell->connections_["\\B"] = sync_value; - mux_set_cell->connections_["\\S"] = sync_high_signals; - mux_set_cell->connections_["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); + mux_set_cell->set("\\A", sig_sr_set); + mux_set_cell->set("\\B", sync_value); + mux_set_cell->set("\\S", sync_high_signals); + mux_set_cell->set("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_clr_cell->connections_["\\A"] = sig_sr_clr; - mux_clr_cell->connections_["\\B"] = sync_value_inv; - mux_clr_cell->connections_["\\S"] = sync_high_signals; - mux_clr_cell->connections_["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); + mux_clr_cell->set("\\A", sig_sr_clr); + mux_clr_cell->set("\\B", sync_value_inv); + mux_clr_cell->set("\\S", sync_high_signals); + mux_clr_cell->set("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); } std::stringstream sstr; @@ -131,11 +131,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; - cell->connections_["\\CLK"] = clk; - cell->connections_["\\SET"] = sig_sr_set; - cell->connections_["\\CLR"] = sig_sr_clr; + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); + cell->set("\\CLK", clk); + cell->set("\\SET", sig_sr_set); + cell->set("\\CLR", sig_sr_clr); log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -155,22 +155,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); - inv_set->connections_["\\A"] = sig_set; - inv_set->connections_["\\Y"] = sig_set_inv; + inv_set->set("\\A", sig_set); + inv_set->set("\\Y", sig_set_inv); RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_set->connections_[set_polarity ? "\\B" : "\\A"] = sig_set; - mux_sr_set->connections_["\\Y"] = sig_sr_set; - mux_sr_set->connections_["\\S"] = set; + mux_sr_set->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); + mux_sr_set->connections()[set_polarity ? "\\B" : "\\A"] = sig_set; + mux_sr_set->set("\\Y", sig_sr_set); + mux_sr_set->set("\\S", set); RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_clr->connections_[set_polarity ? "\\B" : "\\A"] = sig_set_inv; - mux_sr_clr->connections_["\\Y"] = sig_sr_clr; - mux_sr_clr->connections_["\\S"] = set; + mux_sr_clr->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); + mux_sr_clr->connections()[set_polarity ? "\\B" : "\\A"] = sig_set_inv; + mux_sr_clr->set("\\Y", sig_sr_clr); + mux_sr_clr->set("\\S", set); RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; @@ -178,11 +178,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->connections_["\\D"] = sig_in; - cell->connections_["\\Q"] = sig_out; - cell->connections_["\\CLK"] = clk; - cell->connections_["\\SET"] = sig_sr_set; - cell->connections_["\\CLR"] = sig_sr_clr; + cell->set("\\D", sig_in); + cell->set("\\Q", sig_out); + cell->set("\\CLK", clk); + cell->set("\\SET", sig_sr_set); + cell->set("\\CLR", sig_sr_clr); log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -204,11 +204,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ } cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); - cell->connections_["\\D"] = sig_in; - cell->connections_["\\Q"] = sig_out; + cell->set("\\D", sig_in); + cell->set("\\Q", sig_out); if (arst) - cell->connections_["\\ARST"] = *arst; - cell->connections_["\\CLK"] = clk; + cell->set("\\ARST", *arst); + cell->set("\\CLK", clk); log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); if (arst) @@ -296,9 +296,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections_["\\A"] = inputs; - cell->connections_["\\B"] = compare; - cell->connections_["\\Y"] = sync_level->signal; + cell->set("\\A", inputs); + cell->set("\\B", compare); + cell->set("\\Y", sync_level->signal); many_async_rules.clear(); } @@ -322,7 +322,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) if (sync_edge || sync_level || many_async_rules.size() > 0) log_error("Mixed always event with edge and/or level sensitive events!\n"); log(" created direct connection (no actual register cell created).\n"); - mod->connections_.push_back(RTLIL::SigSig(sig, insig)); + mod->connect(RTLIL::SigSig(sig, insig)); continue; } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2cde749a5..2ff755aef 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { - mod->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); + mod->connect(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); } else { @@ -96,9 +96,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - eq_cell->connections_["\\A"] = sig; - eq_cell->connections_["\\B"] = comp; - eq_cell->connections_["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++); + eq_cell->set("\\A", sig); + eq_cell->set("\\B", comp); + eq_cell->set("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); } } @@ -122,8 +122,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - any_cell->connections_["\\A"] = cmp_wire; - any_cell->connections_["\\Y"] = RTLIL::SigSpec(ctrl_wire); + any_cell->set("\\A", cmp_wire); + any_cell->set("\\Y", RTLIL::SigSpec(ctrl_wire)); } return RTLIL::SigSpec(ctrl_wire); @@ -157,10 +157,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); - mux_cell->connections_["\\A"] = else_signal; - mux_cell->connections_["\\B"] = when_signal; - mux_cell->connections_["\\S"] = ctrl_sig; - mux_cell->connections_["\\Y"] = RTLIL::SigSpec(result_wire); + mux_cell->set("\\A", else_signal); + mux_cell->set("\\B", when_signal); + mux_cell->set("\\S", ctrl_sig); + mux_cell->set("\\Y", RTLIL::SigSpec(result_wire)); last_mux_cell = mux_cell; return RTLIL::SigSpec(result_wire); @@ -169,14 +169,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.size() == last_mux_cell->connections_["\\A"].size()); + assert(when_signal.size() == last_mux_cell->get("\\A").size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - last_mux_cell->connections_["\\S"].append(ctrl_sig); - last_mux_cell->connections_["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections_["\\S"].size(); + last_mux_cell->get("\\S").append(ctrl_sig); + last_mux_cell->get("\\B").append(when_signal); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -256,7 +256,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size())); - mod->connections_.push_back(RTLIL::SigSig(sig, value)); + mod->connect(RTLIL::SigSig(sig, value)); } } -- cgit v1.2.3 From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 15:57:57 +0200 Subject: Manual fixes for new cell connections API --- passes/proc/proc_dff.cc | 8 ++++---- passes/proc/proc_mux.cc | 11 +++++++++-- 2 files changed, 13 insertions(+), 6 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 2e2d4701f..cfd2eb7a7 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -160,15 +160,15 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_set->connections()[set_polarity ? "\\B" : "\\A"] = sig_set; + mux_sr_set->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); + mux_sr_set->set(set_polarity ? "\\B" : "\\A", sig_set); mux_sr_set->set("\\Y", sig_sr_set); mux_sr_set->set("\\S", set); RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_clr->connections()[set_polarity ? "\\B" : "\\A"] = sig_set_inv; + mux_sr_clr->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); + mux_sr_clr->set(set_polarity ? "\\B" : "\\A", sig_set_inv); mux_sr_clr->set("\\Y", sig_sr_clr); mux_sr_clr->set("\\S", set); diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2ff755aef..30e7b748b 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -174,8 +174,15 @@ static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - last_mux_cell->get("\\S").append(ctrl_sig); - last_mux_cell->get("\\B").append(when_signal); + + RTLIL::SigSpec new_s = last_mux_cell->get("\\S"); + new_s.append(ctrl_sig); + last_mux_cell->set("\\S", new_s); + + RTLIL::SigSpec new_b = last_mux_cell->get("\\B"); + new_b.append(when_signal); + last_mux_cell->set("\\B", new_b); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size(); } -- cgit v1.2.3 From 946ddff9cef3ea0b4dad8664319fb13074133775 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 20:12:50 +0200 Subject: Changed a lot of code to the new RTLIL::Wire constructors --- passes/proc/proc_mux.cc | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 30e7b748b..67113a682 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -60,10 +60,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); - RTLIL::Wire *cmp_wire = new RTLIL::Wire; - cmp_wire->name = sstr.str() + "_CMP"; - cmp_wire->width = 0; - mod->wires[cmp_wire->name] = cmp_wire; + RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0); for (auto comp : compare) { @@ -109,10 +106,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, } else { - ctrl_wire = new RTLIL::Wire; - ctrl_wire->name = sstr.str() + "_CTRL"; - ctrl_wire->width = 1; - mod->wires[ctrl_wire->name] = ctrl_wire; + ctrl_wire = mod->addWire(sstr.str() + "_CTRL"); // reduce cmp vector to one logic signal RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or"); @@ -147,10 +141,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, assert(ctrl_sig.size() == 1); // prepare multiplexer output signal - RTLIL::Wire *result_wire = new RTLIL::Wire; - result_wire->name = sstr.str() + "_Y"; - result_wire->width = when_signal.size(); - mod->wires[result_wire->name] = result_wire; + RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size()); // create the multiplexer itself RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux"); -- cgit v1.2.3 From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- passes/proc/proc_arst.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 114f2567e..565d86a72 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -243,7 +243,7 @@ struct ProcArstPass : public Pass { if (!design->selected(mod_it.second, proc_it.second)) continue; proc_arst(mod_it.second, proc_it.second, assign_map); - if (global_arst.empty() || mod_it.second->wires.count(global_arst) == 0) + if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0) continue; std::vector arst_actions; for (auto sync : proc_it.second->syncs) @@ -266,7 +266,7 @@ struct ProcArstPass : public Pass { if (!arst_actions.empty()) { RTLIL::SyncRule *sync = new RTLIL::SyncRule; sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; - sync->signal = mod_it.second->wires.at(global_arst); + sync->signal = mod_it.second->wires_.at(global_arst); sync->actions = arst_actions; proc_it.second->syncs.push_back(sync); } -- cgit v1.2.3 From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- passes/proc/proc_arst.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 565d86a72..63d04d351 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -33,7 +33,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp if (signal == ref) return true; - for (auto &cell_it : mod->cells) { + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) return check_signal(mod, cell->get("\\A"), ref, polarity); -- cgit v1.2.3 From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- passes/proc/proc_arst.cc | 2 +- passes/proc/proc_clean.cc | 2 +- passes/proc/proc_dff.cc | 2 +- passes/proc/proc_init.cc | 2 +- passes/proc/proc_mux.cc | 2 +- passes/proc/proc_rmdead.cc | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 63d04d351..e84394770 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -236,7 +236,7 @@ struct ProcArstPass : public Pass { extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { SigMap assign_map(mod_it.second); for (auto &proc_it : mod_it.second->processes) { diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 682515c5e..678d620be 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -149,7 +149,7 @@ struct ProcCleanPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { std::vector delme; if (!design->selected(mod_it.second)) continue; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index cfd2eb7a7..7bd909a68 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -371,7 +371,7 @@ struct ProcDffPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { ConstEval ce(mod_it.second); for (auto &proc_it : mod_it.second->processes) diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 5976c2162..3607905f5 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -101,7 +101,7 @@ struct ProcInitPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &proc_it : mod_it.second->processes) if (design->selected(mod_it.second, proc_it.second)) diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 67113a682..bcbee6cfc 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -276,7 +276,7 @@ struct ProcMuxPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &proc_it : mod_it.second->processes) if (design->selected(mod_it.second, proc_it.second)) diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index d5fbef0d2..e7e4bbc54 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -79,7 +79,7 @@ struct ProcRmdeadPass : public Pass { extra_args(args, 1, design); int total_counter = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; for (auto &proc_it : mod_it.second->processes) { -- cgit v1.2.3 From 49f72421d5ec499da5da713466e058aae2a67436 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:41:42 +0200 Subject: Using new obj iterator API in a few places --- passes/proc/proc_arst.cc | 25 +++++++++++++++---------- passes/proc/proc_clean.cc | 16 ++++++++-------- passes/proc/proc_dff.cc | 12 ++++++------ passes/proc/proc_init.cc | 10 +++++----- passes/proc/proc_mux.cc | 10 +++++----- passes/proc/proc_rmdead.cc | 10 +++++----- 6 files changed, 44 insertions(+), 39 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index e84394770..676469fe2 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -33,20 +33,24 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp if (signal == ref) return true; - for (auto &cell_it : mod->cells_) { - RTLIL::Cell *cell = cell_it.second; + for (auto cell : mod->cells()) + { if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal) return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$logic_not" && cell->get("\\Y") == signal) { polarity = !polarity; return check_signal(mod, cell->get("\\A"), ref, polarity); } + if (cell->type == "$not" && cell->get("\\Y") == signal) { polarity = !polarity; return check_signal(mod, cell->get("\\A"), ref, polarity); } + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) { if (cell->get("\\A").is_fully_const()) { if (!cell->get("\\A").as_bool()) @@ -59,6 +63,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp return check_signal(mod, cell->get("\\A"), ref, polarity); } } + if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) { if (cell->get("\\A").is_fully_const()) { if (cell->get("\\A").as_bool()) @@ -236,14 +241,14 @@ struct ProcArstPass : public Pass { extra_args(args, argidx, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) { - SigMap assign_map(mod_it.second); - for (auto &proc_it : mod_it.second->processes) { - if (!design->selected(mod_it.second, proc_it.second)) + for (auto mod : design->modules()) + if (design->selected(mod)) { + SigMap assign_map(mod); + for (auto &proc_it : mod->processes) { + if (!design->selected(mod, proc_it.second)) continue; - proc_arst(mod_it.second, proc_it.second, assign_map); - if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0) + proc_arst(mod, proc_it.second, assign_map); + if (global_arst.empty() || mod->wire(global_arst) == nullptr) continue; std::vector arst_actions; for (auto sync : proc_it.second->syncs) @@ -266,7 +271,7 @@ struct ProcArstPass : public Pass { if (!arst_actions.empty()) { RTLIL::SyncRule *sync = new RTLIL::SyncRule; sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; - sync->signal = mod_it.second->wires_.at(global_arst); + sync->signal = mod->wire(global_arst); sync->actions = arst_actions; proc_it.second->syncs.push_back(sync); } diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 678d620be..e4c526632 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -149,23 +149,23 @@ struct ProcCleanPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules_) { + for (auto mod : design->modules()) { std::vector delme; - if (!design->selected(mod_it.second)) + if (!design->selected(mod)) continue; - for (auto &proc_it : mod_it.second->processes) { - if (!design->selected(mod_it.second, proc_it.second)) + for (auto &proc_it : mod->processes) { + if (!design->selected(mod, proc_it.second)) continue; - proc_clean(mod_it.second, proc_it.second, total_count); + proc_clean(mod, proc_it.second, total_count); if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 && proc_it.second->root_case.actions.size() == 0) { - log("Removing empty process `%s.%s'.\n", mod_it.first.c_str(), proc_it.second->name.c_str()); + log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str()); delme.push_back(proc_it.first); } } for (auto &id : delme) { - delete mod_it.second->processes[id]; - mod_it.second->processes.erase(id); + delete mod->processes[id]; + mod->processes.erase(id); } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 7bd909a68..dc310bde0 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -371,12 +371,12 @@ struct ProcDffPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) { - ConstEval ce(mod_it.second); - for (auto &proc_it : mod_it.second->processes) - if (design->selected(mod_it.second, proc_it.second)) - proc_dff(mod_it.second, proc_it.second, ce); + for (auto mod : design->modules()) + if (design->selected(mod)) { + ConstEval ce(mod); + for (auto &proc_it : mod->processes) + if (design->selected(mod, proc_it.second)) + proc_dff(mod, proc_it.second, ce); } } } ProcDffPass; diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 3607905f5..99498505f 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -101,11 +101,11 @@ struct ProcInitPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - for (auto &proc_it : mod_it.second->processes) - if (design->selected(mod_it.second, proc_it.second)) - proc_init(mod_it.second, proc_it.second); + for (auto mod : design->modules()) + if (design->selected(mod)) + for (auto &proc_it : mod->processes) + if (design->selected(mod, proc_it.second)) + proc_init(mod, proc_it.second); } } ProcInitPass; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index bcbee6cfc..fb49182c2 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -276,11 +276,11 @@ struct ProcMuxPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - for (auto &proc_it : mod_it.second->processes) - if (design->selected(mod_it.second, proc_it.second)) - proc_mux(mod_it.second, proc_it.second); + for (auto mod : design->modules()) + if (design->selected(mod)) + for (auto &proc_it : mod->processes) + if (design->selected(mod, proc_it.second)) + proc_mux(mod, proc_it.second); } } ProcMuxPass; diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index e7e4bbc54..9e5f413a2 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -79,18 +79,18 @@ struct ProcRmdeadPass : public Pass { extra_args(args, 1, design); int total_counter = 0; - for (auto &mod_it : design->modules_) { - if (!design->selected(mod_it.second)) + for (auto mod : design->modules()) { + if (!design->selected(mod)) continue; - for (auto &proc_it : mod_it.second->processes) { - if (!design->selected(mod_it.second, proc_it.second)) + for (auto &proc_it : mod->processes) { + if (!design->selected(mod, proc_it.second)) continue; int counter = 0; for (auto switch_it : proc_it.second->root_case.switches) proc_rmdead(switch_it, counter); if (counter > 0) log("Removed %d dead cases from process %s in module %s.\n", counter, - proc_it.first.c_str(), mod_it.first.c_str()); + proc_it.first.c_str(), log_id(mod)); total_counter += counter; } } -- cgit v1.2.3 From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- passes/proc/proc_dff.cc | 3 +-- passes/proc/proc_init.cc | 2 +- passes/proc/proc_mux.cc | 13 ++++++------- passes/proc/proc_rmdead.cc | 1 - 4 files changed, 8 insertions(+), 11 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index dc310bde0..91cafe3be 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -24,7 +24,6 @@ #include #include #include -#include static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) { @@ -288,7 +287,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } - assert(inputs.size() == compare.size()); + log_assert(inputs.size() == compare.size()); RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 99498505f..c72840c02 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -25,7 +25,7 @@ static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule) { - assert(rule.compare.size() == 0); + log_assert(rule.compare.size() == 0); while (1) { RTLIL::SigSpec tmp = sig; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index fb49182c2..e7661245e 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -23,7 +23,6 @@ #include #include #include -#include static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs) { @@ -67,7 +66,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, RTLIL::SigSpec sig = signal; // get rid of don't-care bits - assert(sig.size() == comp.size()); + log_assert(sig.size() == comp.size()); for (int i = 0; i < comp.size(); i++) if (comp[i] == RTLIL::State::Sa) { sig.remove(i); @@ -125,7 +124,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw) { - assert(when_signal.size() == else_signal.size()); + log_assert(when_signal.size() == else_signal.size()); std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); @@ -138,7 +137,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); if (ctrl_sig.size() == 0) return when_signal; - assert(ctrl_sig.size() == 1); + log_assert(ctrl_sig.size() == 1); // prepare multiplexer output signal RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size()); @@ -159,11 +158,11 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { - assert(last_mux_cell != NULL); - assert(when_signal.size() == last_mux_cell->get("\\A").size()); + log_assert(last_mux_cell != NULL); + log_assert(when_signal.size() == last_mux_cell->get("\\A").size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - assert(ctrl_sig.size() == 1); + log_assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; RTLIL::SigSpec new_s = last_mux_cell->get("\\S"); diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 9e5f413a2..61844d5eb 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -23,7 +23,6 @@ #include #include #include -#include #include static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) -- cgit v1.2.3 From 1cb25c05b37b0172dbc50e140fe20f25d973dd8a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 13:19:47 +0200 Subject: Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace --- passes/proc/proc_dff.cc | 6 +++--- passes/proc/proc_mux.cc | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 91cafe3be..d894b442b 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -122,7 +122,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S } std::stringstream sstr; - sstr << "$procdff$" << (RTLIL::autoidx++); + sstr << "$procdff$" << (autoidx++); RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; @@ -144,7 +144,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc) { std::stringstream sstr; - sstr << "$procdff$" << (RTLIL::autoidx++); + sstr << "$procdff$" << (autoidx++); RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size()); RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); @@ -191,7 +191,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc) { std::stringstream sstr; - sstr << "$procdff$" << (RTLIL::autoidx++); + sstr << "$procdff$" << (autoidx++); RTLIL::Cell *cell = mod->addCell(sstr.str(), arst ? "$adff" : "$dff"); cell->attributes = proc->attributes; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index e7661245e..b18ce4925 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -57,7 +57,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig) static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SwitchRule *sw) { std::stringstream sstr; - sstr << "$procmux$" << (RTLIL::autoidx++); + sstr << "$procmux$" << (autoidx++); RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0); @@ -127,7 +127,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, log_assert(when_signal.size() == else_signal.size()); std::stringstream sstr; - sstr << "$procmux$" << (RTLIL::autoidx++); + sstr << "$procmux$" << (autoidx++); // the trivial cases if (compare.size() == 0 || when_signal == else_signal) -- cgit v1.2.3 From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 16:38:54 +0200 Subject: Renamed port access function on RTLIL::Cell, added param access functions --- passes/proc/proc_arst.cc | 44 ++++++++++++------------ passes/proc/proc_dff.cc | 88 ++++++++++++++++++++++++------------------------ passes/proc/proc_mux.cc | 30 ++++++++--------- 3 files changed, 81 insertions(+), 81 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 676469fe2..f11b328f0 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -35,45 +35,45 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp for (auto cell : mod->cells()) { - if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) - return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal) + return check_signal(mod, cell->getPort("\\A"), ref, polarity); - if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal) - return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal) + return check_signal(mod, cell->getPort("\\A"), ref, polarity); - if (cell->type == "$logic_not" && cell->get("\\Y") == signal) { + if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) { polarity = !polarity; - return check_signal(mod, cell->get("\\A"), ref, polarity); + return check_signal(mod, cell->getPort("\\A"), ref, polarity); } - if (cell->type == "$not" && cell->get("\\Y") == signal) { + if (cell->type == "$not" && cell->getPort("\\Y") == signal) { polarity = !polarity; - return check_signal(mod, cell->get("\\A"), ref, polarity); + return check_signal(mod, cell->getPort("\\A"), ref, polarity); } - if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) { - if (cell->get("\\A").is_fully_const()) { - if (!cell->get("\\A").as_bool()) + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) { + if (cell->getPort("\\A").is_fully_const()) { + if (!cell->getPort("\\A").as_bool()) polarity = !polarity; - return check_signal(mod, cell->get("\\B"), ref, polarity); + return check_signal(mod, cell->getPort("\\B"), ref, polarity); } - if (cell->get("\\B").is_fully_const()) { - if (!cell->get("\\B").as_bool()) + if (cell->getPort("\\B").is_fully_const()) { + if (!cell->getPort("\\B").as_bool()) polarity = !polarity; - return check_signal(mod, cell->get("\\A"), ref, polarity); + return check_signal(mod, cell->getPort("\\A"), ref, polarity); } } - if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) { - if (cell->get("\\A").is_fully_const()) { - if (cell->get("\\A").as_bool()) + if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) { + if (cell->getPort("\\A").is_fully_const()) { + if (cell->getPort("\\A").as_bool()) polarity = !polarity; - return check_signal(mod, cell->get("\\B"), ref, polarity); + return check_signal(mod, cell->getPort("\\B"), ref, polarity); } - if (cell->get("\\B").is_fully_const()) { - if (cell->get("\\B").as_bool()) + if (cell->getPort("\\B").is_fully_const()) { + if (cell->getPort("\\B").as_bool()) polarity = !polarity; - return check_signal(mod, cell->get("\\A"), ref, polarity); + return check_signal(mod, cell->getPort("\\A"), ref, polarity); } } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index d894b442b..e69e8023d 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -76,8 +76,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->set("\\A", sync_low_signals); - cell->set("\\Y", sync_low_signals = mod->addWire(NEW_ID)); + cell->setPort("\\A", sync_low_signals); + cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID)); } if (sync_low_signals.size() > 0) { @@ -85,9 +85,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->set("\\A", sync_low_signals); - cell->set("\\Y", mod->addWire(NEW_ID)); - sync_high_signals.append(cell->get("\\Y")); + cell->setPort("\\A", sync_low_signals); + cell->setPort("\\Y", mod->addWire(NEW_ID)); + sync_high_signals.append(cell->getPort("\\Y")); } if (sync_high_signals.size() > 1) { @@ -95,30 +95,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->set("\\A", sync_high_signals); - cell->set("\\Y", sync_high_signals = mod->addWire(NEW_ID)); + cell->setPort("\\A", sync_high_signals); + cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID)); } RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); - inv_cell->set("\\A", sync_value); - inv_cell->set("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); + inv_cell->setPort("\\A", sync_value); + inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_set_cell->set("\\A", sig_sr_set); - mux_set_cell->set("\\B", sync_value); - mux_set_cell->set("\\S", sync_high_signals); - mux_set_cell->set("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); + mux_set_cell->setPort("\\A", sig_sr_set); + mux_set_cell->setPort("\\B", sync_value); + mux_set_cell->setPort("\\S", sync_high_signals); + mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_clr_cell->set("\\A", sig_sr_clr); - mux_clr_cell->set("\\B", sync_value_inv); - mux_clr_cell->set("\\S", sync_high_signals); - mux_clr_cell->set("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); + mux_clr_cell->setPort("\\A", sig_sr_clr); + mux_clr_cell->setPort("\\B", sync_value_inv); + mux_clr_cell->setPort("\\S", sync_high_signals); + mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); } std::stringstream sstr; @@ -130,11 +130,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); - cell->set("\\CLK", clk); - cell->set("\\SET", sig_sr_set); - cell->set("\\CLR", sig_sr_clr); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); + cell->setPort("\\CLK", clk); + cell->setPort("\\SET", sig_sr_set); + cell->setPort("\\CLR", sig_sr_clr); log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -154,22 +154,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); - inv_set->set("\\A", sig_set); - inv_set->set("\\Y", sig_set_inv); + inv_set->setPort("\\A", sig_set); + inv_set->setPort("\\Y", sig_set_inv); RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); - mux_sr_set->set(set_polarity ? "\\B" : "\\A", sig_set); - mux_sr_set->set("\\Y", sig_sr_set); - mux_sr_set->set("\\S", set); + mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); + mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set); + mux_sr_set->setPort("\\Y", sig_sr_set); + mux_sr_set->setPort("\\S", set); RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); - mux_sr_clr->set(set_polarity ? "\\B" : "\\A", sig_set_inv); - mux_sr_clr->set("\\Y", sig_sr_clr); - mux_sr_clr->set("\\S", set); + mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); + mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv); + mux_sr_clr->setPort("\\Y", sig_sr_clr); + mux_sr_clr->setPort("\\S", set); RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; @@ -177,11 +177,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->set("\\D", sig_in); - cell->set("\\Q", sig_out); - cell->set("\\CLK", clk); - cell->set("\\SET", sig_sr_set); - cell->set("\\CLR", sig_sr_clr); + cell->setPort("\\D", sig_in); + cell->setPort("\\Q", sig_out); + cell->setPort("\\CLK", clk); + cell->setPort("\\SET", sig_sr_set); + cell->setPort("\\CLR", sig_sr_clr); log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -203,11 +203,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ } cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); - cell->set("\\D", sig_in); - cell->set("\\Q", sig_out); + cell->setPort("\\D", sig_in); + cell->setPort("\\Q", sig_out); if (arst) - cell->set("\\ARST", *arst); - cell->set("\\CLK", clk); + cell->setPort("\\ARST", *arst); + cell->setPort("\\CLK", clk); log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); if (arst) @@ -295,9 +295,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->set("\\A", inputs); - cell->set("\\B", compare); - cell->set("\\Y", sync_level->signal); + cell->setPort("\\A", inputs); + cell->setPort("\\B", compare); + cell->setPort("\\Y", sync_level->signal); many_async_rules.clear(); } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index b18ce4925..c00b00a2a 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -92,9 +92,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - eq_cell->set("\\A", sig); - eq_cell->set("\\B", comp); - eq_cell->set("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); + eq_cell->setPort("\\A", sig); + eq_cell->setPort("\\B", comp); + eq_cell->setPort("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); } } @@ -115,8 +115,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - any_cell->set("\\A", cmp_wire); - any_cell->set("\\Y", RTLIL::SigSpec(ctrl_wire)); + any_cell->setPort("\\A", cmp_wire); + any_cell->setPort("\\Y", RTLIL::SigSpec(ctrl_wire)); } return RTLIL::SigSpec(ctrl_wire); @@ -147,10 +147,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); - mux_cell->set("\\A", else_signal); - mux_cell->set("\\B", when_signal); - mux_cell->set("\\S", ctrl_sig); - mux_cell->set("\\Y", RTLIL::SigSpec(result_wire)); + mux_cell->setPort("\\A", else_signal); + mux_cell->setPort("\\B", when_signal); + mux_cell->setPort("\\S", ctrl_sig); + mux_cell->setPort("\\Y", RTLIL::SigSpec(result_wire)); last_mux_cell = mux_cell; return RTLIL::SigSpec(result_wire); @@ -159,21 +159,21 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { log_assert(last_mux_cell != NULL); - log_assert(when_signal.size() == last_mux_cell->get("\\A").size()); + log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); log_assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - RTLIL::SigSpec new_s = last_mux_cell->get("\\S"); + RTLIL::SigSpec new_s = last_mux_cell->getPort("\\S"); new_s.append(ctrl_sig); - last_mux_cell->set("\\S", new_s); + last_mux_cell->setPort("\\S", new_s); - RTLIL::SigSpec new_b = last_mux_cell->get("\\B"); + RTLIL::SigSpec new_b = last_mux_cell->getPort("\\B"); new_b.append(when_signal); - last_mux_cell->set("\\B", new_b); + last_mux_cell->setPort("\\B", new_b); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size(); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) -- cgit v1.2.3 From b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 13:11:01 +0200 Subject: More cleanups related to RTLIL::IdString usage --- passes/proc/proc_clean.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index e4c526632..13be0ddb6 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -150,7 +150,7 @@ struct ProcCleanPass : public Pass { extra_args(args, 1, design); for (auto mod : design->modules()) { - std::vector delme; + std::vector delme; if (!design->selected(mod)) continue; for (auto &proc_it : mod->processes) { -- cgit v1.2.3 From 9d353fc543295db7d6f4b4ba60c2b66a509b3ee2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Aug 2014 17:35:22 +0200 Subject: Fixed handling of constant-true branches in proc_clean --- passes/proc/proc_clean.cc | 3 ++- passes/proc/proc_rmdead.cc | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'passes/proc') diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 13be0ddb6..1e3dd9ce7 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -59,7 +59,8 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did sw->signal = RTLIL::SigSpec(); } - if (sw->cases.size() == 1 && (sw->signal.size() == 0 || sw->cases[0]->compare.empty())) + if (parent->switches.front() == sw && sw->cases.size() == 1 && + (sw->signal.size() == 0 || sw->cases[0]->compare.empty())) { did_something = true; for (auto &action : sw->cases[0]->actions) diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 61844d5eb..fe3532da8 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -31,7 +31,7 @@ static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = sw->cases[i]->compare.size() == 0 && !pool.empty(); + bool is_default = SIZE(sw->cases[i]->compare) == 0 && (!pool.empty() || SIZE(sw->signal) == 0); for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; -- cgit v1.2.3