From b0ad2592befb1a5b5a41319f6d75773aea202173 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 12:04:16 -0700 Subject: Run until convergence --- passes/pmgen/xilinx_dsp.cc | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'passes/pmgen/xilinx_dsp.cc') diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 0d0c60375..7530eb5ad 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -24,6 +24,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +bool did_something; + #include "passes/pmgen/xilinx_dsp_pm.h" #include "passes/pmgen/xilinx_dsp_cascade_pm.h" @@ -509,7 +511,7 @@ struct XilinxDspPass : public Pass { log("be added to the multiplier result to form the next accumulation result.\n"); log("\n"); log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n"); - log("connections (optionally, where 'P' is right-shifted by 18-bits and used as an\n"); + log("connections (optionally, where 'P' is right-shifted by 17-bits and used as an\n"); log("input to the post-adder -- a pattern common for summing partial products to\n"); log("implement wide multipliers).\n"); log("\n"); @@ -545,8 +547,12 @@ struct XilinxDspPass : public Pass { xilinx_dsp_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_pack(pack_xilinx_dsp); - xilinx_dsp_cascade_pm pmc(module, module->selected_cells()); - pmc.run_xilinx_dsp_cascade(); + do { + did_something = false; + xilinx_dsp_cascade_pm pmc(module, module->selected_cells()); + pmc.run_xilinx_dsp_cascadeP(); + pmc.run_xilinx_dsp_cascadeAB(); + } while (did_something); } } } XilinxDspPass; -- cgit v1.2.3