From 43081337fa4a85cd4a1a007576eaf945816bd576 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 16:04:21 -0700
Subject: Cleanup opt_expr.cc

---
 passes/opt/opt_expr.cc | 65 +++++++++++++++++++++++---------------------------
 1 file changed, 30 insertions(+), 35 deletions(-)

(limited to 'passes/opt')

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 512ef0cbf..ef4b8b57a 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -367,10 +367,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 	for (auto cell : module->cells())
 		if (design->selected(module, cell) && cell->type[0] == '$') {
-			if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") &&
+			if (cell->type.in("$_NOT_", "$not", "$logic_not") &&
 					cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1)
 				invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A"));
-			if ((cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == SigSpec(State::S1) && cell->getPort("\\B") == SigSpec(State::S0))
+			if (cell->type.in("$mux", "$_MUX_") &&
+					cell->getPort("\\A") == SigSpec(State::S1) && cell->getPort("\\B") == SigSpec(State::S0))
 				invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\S"));
 			if (ct_combinational.cell_known(cell->type))
 				for (auto &conn : cell->connections()) {
@@ -512,13 +513,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 		if (do_fine)
 		{
-			if (cell->type == "$not" || cell->type == "$pos" ||
-					cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor")
+			if (cell->type.in("$not", "$pos", "$and", "$or", "$xor", "$xnor"))
 				if (group_cell_inputs(module, cell, true, assign_map))
 					goto next_cell;
 
-			if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" ||
-					cell->type == "$reduce_or" || cell->type == "$reduce_and" || cell->type == "$reduce_bool")
+			if (cell->type.in("$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_and", "$reduce_bool"))
 			{
 				SigBit neutral_bit = cell->type == "$reduce_and" ? State::S1 : State::S0;
 
@@ -541,7 +540,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type == "$logic_and" || cell->type == "$logic_or")
+			if (cell->type.in("$logic_and", "$logic_or"))
 			{
 				SigBit neutral_bit = State::S0;
 
@@ -590,7 +589,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool")
+			if (cell->type.in("$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool"))
 			{
 				RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 
@@ -616,7 +615,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				}
 			}
 
-			if (cell->type == "$logic_and" || cell->type == "$logic_or")
+			if (cell->type.in("$logic_and", "$logic_or"))
 			{
 				RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
 
@@ -643,16 +642,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" ||
-				cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" ||
-				cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt" ||
-				cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" ||
-				cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
+		if (cell->type.in("$reduce_xor", "$reduce_xnor", "$shift", "$shiftx", "$shl", "$shr", "$sshl", "$sshr",
+					"$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow"))
 		{
 			RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 			RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec();
 
-			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
+			if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx"))
 				sig_a = RTLIL::SigSpec();
 
 			for (auto &bit : sig_a.to_sigbit_vector())
@@ -667,8 +663,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		found_the_x_bit:
 				cover_list("opt.opt_expr.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
 						"$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str());
-				if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" ||
-						cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
+				if (cell->type.in("$reduce_xor", "$reduce_xnor", "$lt", "$le", "$ge", "$gt"))
 					replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
 				else
 					replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort("\\Y").size()));
@@ -676,14 +671,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 &&
+		if (cell->type.in("$_NOT_", "$not", "$logic_not") && cell->getPort("\\Y").size() == 1 &&
 				invert_map.count(assign_map(cell->getPort("\\A"))) != 0) {
 			cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());
 			replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A"))));
 			goto next_cell;
 		}
 
-		if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) {
+		if (cell->type.in("$_MUX_", "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) {
 			cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
 			log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
 			RTLIL::SigSpec tmp = cell->getPort("\\A");
@@ -786,7 +781,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if (cell->type == "$_TBUF_" || cell->type == "$tribuf") {
+		if (cell->type.in("$_TBUF_", "$tribuf")) {
 			RTLIL::SigSpec input = cell->getPort(cell->type == "$_TBUF_" ? "\\E" : "\\EN");
 			RTLIL::SigSpec a = cell->getPort("\\A");
 			assign_map.apply(input);
@@ -803,7 +798,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex")
+		if (cell->type.in("$eq", "$ne", "$eqx", "$nex"))
 		{
 			RTLIL::SigSpec a = cell->getPort("\\A");
 			RTLIL::SigSpec b = cell->getPort("\\B");
@@ -820,7 +815,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			for (int i = 0; i < GetSize(a); i++) {
 				if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
 					cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
-					RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S0 : RTLIL::State::S1);
+					RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in("$eq", "$eqx") ?  RTLIL::State::S0 : RTLIL::State::S1);
 					new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false);
 					replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y);
 					goto next_cell;
@@ -833,7 +828,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 			if (new_a.size() == 0) {
 				cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
-				RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S1 : RTLIL::State::S0);
+				RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in("$eq", "$eqx") ?  RTLIL::State::S1 : RTLIL::State::S0);
 				new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false);
 				replace_cell(assign_map, module, cell, "empty", "\\Y", new_y);
 				goto next_cell;
@@ -848,7 +843,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
+		if (cell->type.in("$eq", "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
 				cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
 		{
 			RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
@@ -878,7 +873,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if ((cell->type == "$eq" || cell->type == "$ne") &&
+		if (cell->type.in("$eq", "$ne") &&
 				(assign_map(cell->getPort("\\A")).is_fully_zero() || assign_map(cell->getPort("\\B")).is_fully_zero()))
 		{
 			cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str());
@@ -937,7 +932,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			bool identity_wrt_b = false;
 			bool arith_inverse = false;
 
-			if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor")
+			if (cell->type.in("$add", "$sub", "$or", "$xor"))
 			{
 				RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
 				RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
@@ -949,7 +944,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					identity_wrt_a = true;
 			}
 
-			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
+			if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx"))
 			{
 				RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
 
@@ -1004,15 +999,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
-				cell->getPort("\\A") == RTLIL::SigSpec(0, 1) && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
+		if (mux_bool && cell->type.in("$mux", "$_MUX_") &&
+				cell->getPort("\\A") == State::S0 && cell->getPort("\\B") == State::S1) {
 			cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str());
 			replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S"));
 			goto next_cell;
 		}
 
-		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
-				cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) {
+		if (mux_bool && cell->type.in("$mux", "$_MUX_") &&
+				cell->getPort("\\A") == State::S1 && cell->getPort("\\B") == State::S0) {
 			cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str());
 			log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
 			cell->setPort("\\A", cell->getPort("\\S"));
@@ -1031,7 +1026,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) {
+		if (consume_x && mux_bool && cell->type.in("$mux", "$_MUX_") && cell->getPort("\\A") == State::S0) {
 			cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str());
 			log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
 			cell->setPort("\\A", cell->getPort("\\S"));
@@ -1051,7 +1046,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
+		if (consume_x && mux_bool && cell->type.in("$mux", "$_MUX_") && cell->getPort("\\B") == State::S1) {
 			cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str());
 			log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
 			cell->setPort("\\B", cell->getPort("\\S"));
@@ -1071,7 +1066,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			goto next_cell;
 		}
 
-		if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
+		if (mux_undef && cell->type.in("$mux", "$pmux")) {
 			RTLIL::SigSpec new_a, new_b, new_s;
 			int width = cell->getPort("\\A").size();
 			if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) ||
@@ -1413,7 +1408,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		}
 
 		// simplify comparisons
-		if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
+		if (do_fine && cell->type.in("$lt", "$ge", "$gt", "$le"))
 		{
 			IdString cmp_type = cell->type;
 			SigSpec var_sig = cell->getPort("\\A");
-- 
cgit v1.2.3


From 3486235338faa1377bb4e1a8981a45b4ee6edfa9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 16:18:18 -0700
Subject: Make liberal use of IdString.in()

---
 passes/opt/opt_merge.cc   | 8 ++++----
 passes/opt/opt_muxtree.cc | 2 +-
 passes/opt/opt_rmdff.cc   | 6 +++---
 passes/opt/share.cc       | 4 ++--
 4 files changed, 10 insertions(+), 10 deletions(-)

(limited to 'passes/opt')

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 7567d4657..8964171e6 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -94,8 +94,8 @@ struct OptMergeWorker
 		const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
 		dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
 
-		if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
-				cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
+		if (cell->type.in("$and", "$or", "$xor", "$xnor", "$add", "$mul",
+				"$logic_and", "$logic_or", "$_AND_", "$_OR_", "$_XOR_")) {
 			alt_conn = *conn;
 			if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
 				alt_conn["\\A"] = conn->at("\\B");
@@ -103,13 +103,13 @@ struct OptMergeWorker
 			}
 			conn = &alt_conn;
 		} else
-		if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") {
+		if (cell->type.in("$reduce_xor", "$reduce_xnor")) {
 			alt_conn = *conn;
 			assign_map.apply(alt_conn.at("\\A"));
 			alt_conn.at("\\A").sort();
 			conn = &alt_conn;
 		} else
-		if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") {
+		if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) {
 			alt_conn = *conn;
 			assign_map.apply(alt_conn.at("\\A"));
 			alt_conn.at("\\A").sort_and_unify();
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 6511e091b..4b96fe524 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -84,7 +84,7 @@ struct OptMuxtreeWorker
 		//	.const_deactivated
 		for (auto cell : module->cells())
 		{
-			if (cell->type == "$mux" || cell->type == "$pmux")
+			if (cell->type.in("$mux", "$pmux"))
 			{
 				RTLIL::SigSpec sig_a = cell->getPort("\\A");
 				RTLIL::SigSpec sig_b = cell->getPort("\\B");
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index be6ac2d30..d712736c1 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -71,7 +71,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 		pol_set = cell->type[12] == 'P' ? State::S1 : State::S0;
 		pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
 	} else
-	if (cell->type == "$dffsr" || cell->type == "$dlatchsr") {
+	if (cell->type.in("$dffsr", "$dlatchsr")) {
 		pol_set = cell->parameters["\\SET_POLARITY"].as_bool() ? State::S1 : State::S0;
 		pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool() ? State::S1 : State::S0;
 	} else
@@ -137,7 +137,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == "$dffsr" || cell->type == "$dlatchsr")
+	if (cell->type.in("$dffsr", "$dlatchsr"))
 	{
 		cell->setParam("\\WIDTH", GetSize(sig_d));
 		cell->setPort("\\SET", sig_set);
@@ -624,7 +624,7 @@ struct OptRmdffPass : public Pass {
 						}
 				}
 
-				if (cell->type == "$mux" || cell->type == "$pmux") {
+				if (cell->type.in("$mux", "$pmux")) {
 					if (cell->getPort("\\A").size() == cell->getPort("\\B").size())
 						mux_drivers.insert(assign_map(cell->getPort("\\Y")), cell);
 					continue;
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index c85c27427..7f66f749f 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -376,13 +376,13 @@ struct ShareWorker
 				continue;
 			}
 
-			if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") {
+			if (cell->type.in("$mul", "$div", "$mod")) {
 				if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4)
 					shareable_cells.insert(cell);
 				continue;
 			}
 
-			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
+			if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) {
 				if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8)
 					shareable_cells.insert(cell);
 				continue;
-- 
cgit v1.2.3


From e38f40af5b7cdd5c8b896ffba17069bd65f01f29 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 16:42:25 -0700
Subject: Use IdString::begins_with()

---
 passes/opt/opt_rmdff.cc | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'passes/opt')

diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index d712736c1..450626f4a 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -63,11 +63,11 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 
 	log_assert(GetSize(sig_set) == GetSize(sig_clr));
 
-	if (cell->type.substr(0,8) == "$_DFFSR_") {
+	if (cell->type.begins_with("$_DFFSR_")) {
 		pol_set = cell->type[9] == 'P' ? State::S1 : State::S0;
 		pol_clr = cell->type[10] == 'P' ? State::S1 : State::S0;
 	} else
-	if (cell->type.substr(0,11) == "$_DLATCHSR_") {
+	if (cell->type.begins_with("$_DLATCHSR_")) {
 		pol_set = cell->type[12] == 'P' ? State::S1 : State::S0;
 		pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
 	} else
@@ -198,9 +198,9 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 	{
 		IdString new_type;
 
-		if (cell->type.substr(0,8) == "$_DFFSR_")
+		if (cell->type.begins_with("$_DFFSR_"))
 			new_type = stringf("$_DFF_%c_", cell->type[8]);
-		else if (cell->type.substr(0,11) == "$_DLATCHSR_")
+		else if (cell->type.begins_with("$_DLATCHSR_"))
 			new_type = stringf("$_DLATCH_%c_", cell->type[11]);
 		else
 			log_abort();
@@ -278,7 +278,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		sig_c = dff->getPort("\\C");
 		val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
 	}
-	else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" &&
+	else if (dff->type.begins_with("$_DFF_") && dff->type.substr(9) == "_" &&
 			(dff->type[6] == 'N' || dff->type[6] == 'P') &&
 			(dff->type[7] == 'N' || dff->type[7] == 'P') &&
 			(dff->type[8] == '0' || dff->type[8] == '1')) {
@@ -290,7 +290,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
 		val_rv = RTLIL::Const(dff->type[8] == '1', 1);
 	}
-	else if (dff->type.substr(0,7) == "$_DFFE_" && dff->type.substr(9) == "_" &&
+	else if (dff->type.begins_with("$_DFFE_") && dff->type.substr(9) == "_" &&
 			(dff->type[7] == 'N' || dff->type[7] == 'P') &&
 			(dff->type[8] == 'N' || dff->type[8] == 'P')) {
 		sig_d = dff->getPort("\\D");
@@ -428,7 +428,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 			return true;
 		}
 
-		log_assert(dff->type.substr(0,6) == "$_DFF_");
+		log_assert(dff->type.begins_with("$_DFF_"));
 		dff->type = stringf("$_DFF_%c_", + dff->type[6]);
 		dff->unsetPort("\\R");
 	}
@@ -452,7 +452,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 			return true;
 		}
 
-		log_assert(dff->type.substr(0,7) == "$_DFFE_");
+		log_assert(dff->type.begins_with("$_DFFE_"));
 		dff->type = stringf("$_DFF_%c_", + dff->type[7]);
 		dff->unsetPort("\\E");
 	}
-- 
cgit v1.2.3


From c11ad24fd7d961432cfdbca7497ba229d3b4f38d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 16:45:48 -0700
Subject: Use std::stoi instead of atoi(<str>.c_str())

---
 passes/opt/opt_lut.cc     | 4 ++--
 passes/opt/pmux2shiftx.cc | 4 ++--
 passes/opt/share.cc       | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'passes/opt')

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 587ef878a..6d97c0bb4 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -555,14 +555,14 @@ struct OptLutPass : public Pass {
 					if (conn_tokens.size() != 2)
 						log_cmd_error("Invalid format of -dlogic signal mapping.\n");
 					IdString logic_port = "\\" + conn_tokens[0];
-					int lut_input = atoi(conn_tokens[1].c_str());
+					int lut_input = std::stoi(conn_tokens[1]);
 					dlogic[type][lut_input] = logic_port;
 				}
 				continue;
 			}
 			if (args[argidx] == "-limit" && argidx + 1 < args.size())
 			{
-				limit = atoi(args[++argidx].c_str());
+				limit = std::stoi(args[++argidx]);
 				continue;
 			}
 			break;
diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index 65d8b8f32..e571ed3c6 100644
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -240,11 +240,11 @@ struct Pmux2ShiftxPass : public Pass {
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			if (args[argidx] == "-min_density" && argidx+1 < args.size()) {
-				min_density = atoi(args[++argidx].c_str());
+				min_density = std::stoi(args[++argidx]);
 				continue;
 			}
 			if (args[argidx] == "-min_choices" && argidx+1 < args.size()) {
-				min_choices = atoi(args[++argidx].c_str());
+				min_choices = std::stoi(args[++argidx]);
 				continue;
 			}
 			if (args[argidx] == "-onehot" && argidx+1 < args.size() && args[argidx+1] == "ignore") {
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 7f66f749f..ea5bf8d33 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -1521,7 +1521,7 @@ struct SharePass : public Pass {
 				continue;
 			}
 			if (args[argidx] == "-limit" && argidx+1 < args.size()) {
-				config.limit = atoi(args[++argidx].c_str());
+				config.limit = std::stoi(args[++argidx]);
 				continue;
 			}
 			break;
-- 
cgit v1.2.3


From 48d0f994064557dc0832748e17133ee2eac88cbf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 11:09:17 -0700
Subject: stoi -> atoi

---
 passes/opt/opt_lut.cc     | 4 ++--
 passes/opt/pmux2shiftx.cc | 4 ++--
 passes/opt/share.cc       | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'passes/opt')

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 6d97c0bb4..587ef878a 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -555,14 +555,14 @@ struct OptLutPass : public Pass {
 					if (conn_tokens.size() != 2)
 						log_cmd_error("Invalid format of -dlogic signal mapping.\n");
 					IdString logic_port = "\\" + conn_tokens[0];
-					int lut_input = std::stoi(conn_tokens[1]);
+					int lut_input = atoi(conn_tokens[1].c_str());
 					dlogic[type][lut_input] = logic_port;
 				}
 				continue;
 			}
 			if (args[argidx] == "-limit" && argidx + 1 < args.size())
 			{
-				limit = std::stoi(args[++argidx]);
+				limit = atoi(args[++argidx].c_str());
 				continue;
 			}
 			break;
diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index e571ed3c6..65d8b8f32 100644
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -240,11 +240,11 @@ struct Pmux2ShiftxPass : public Pass {
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			if (args[argidx] == "-min_density" && argidx+1 < args.size()) {
-				min_density = std::stoi(args[++argidx]);
+				min_density = atoi(args[++argidx].c_str());
 				continue;
 			}
 			if (args[argidx] == "-min_choices" && argidx+1 < args.size()) {
-				min_choices = std::stoi(args[++argidx]);
+				min_choices = atoi(args[++argidx].c_str());
 				continue;
 			}
 			if (args[argidx] == "-onehot" && argidx+1 < args.size() && args[argidx+1] == "ignore") {
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index ea5bf8d33..7f66f749f 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -1521,7 +1521,7 @@ struct SharePass : public Pass {
 				continue;
 			}
 			if (args[argidx] == "-limit" && argidx+1 < args.size()) {
-				config.limit = std::stoi(args[++argidx]);
+				config.limit = atoi(args[++argidx].c_str());
 				continue;
 			}
 			break;
-- 
cgit v1.2.3


From 71649969213863b2695f1c51956886fc7879c3e6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 11:12:38 -0700
Subject: RTLIL::S{0,1} -> State::S{0,1}

---
 passes/opt/muxpack.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/opt')

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 6697d6ca1..225c30d9a 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -49,7 +49,7 @@ struct ExclusiveDatabase
 			}
 			else if (cell->type == "$logic_not") {
 				nonconst_sig = sigmap(cell->getPort("\\A"));
-				const_sig = Const(RTLIL::S0, GetSize(nonconst_sig));
+				const_sig = Const(State::S0, GetSize(nonconst_sig));
 				y_port = sigmap(cell->getPort("\\Y"));
 			}
 			else if (cell->type == "$reduce_or") {
-- 
cgit v1.2.3


From 6d77236f3845cd8785e7bdd4da3c5ef966be6043 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 12:20:08 -0700
Subject: substr() -> compare()

---
 passes/opt/opt_clean.cc | 6 +++---
 passes/opt/opt_merge.cc | 2 +-
 passes/opt/opt_rmdff.cc | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'passes/opt')

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index a8a8e0bc7..905c95b6c 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -222,10 +222,10 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
 
 bool check_public_name(RTLIL::IdString id)
 {
-	const std::string &id_str = id.str();
-	if (id_str[0] == '$')
+	if (id.begins_with("$"))
 		return false;
-	if (id_str.substr(0, 2) == "\\_" && (id_str[id_str.size()-1] == '_' || id_str.find("_[") != std::string::npos))
+	const std::string &id_str = id.str();
+	if (id.begins_with("\\_") && (id.ends_with("_") || id_str.find("_[") != std::string::npos))
 		return false;
 	if (id_str.find(".$") != std::string::npos)
 		return false;
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 8964171e6..cac7c0a6f 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -222,7 +222,7 @@ struct OptMergeWorker
 			return true;
 		}
 
-		if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
+		if (cell1->type.begins_with("$") && conn1.count("\\Q") != 0) {
 			std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector();
 			std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector();
 			for (size_t i = 0; i < q1.size(); i++)
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 450626f4a..8d42a37c3 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -278,7 +278,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		sig_c = dff->getPort("\\C");
 		val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
 	}
-	else if (dff->type.begins_with("$_DFF_") && dff->type.substr(9) == "_" &&
+	else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 &&
 			(dff->type[6] == 'N' || dff->type[6] == 'P') &&
 			(dff->type[7] == 'N' || dff->type[7] == 'P') &&
 			(dff->type[8] == '0' || dff->type[8] == '1')) {
@@ -290,7 +290,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
 		val_rv = RTLIL::Const(dff->type[8] == '1', 1);
 	}
-	else if (dff->type.begins_with("$_DFFE_") && dff->type.substr(9) == "_" &&
+	else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 &&
 			(dff->type[7] == 'N' || dff->type[7] == 'P') &&
 			(dff->type[8] == 'N' || dff->type[8] == 'P')) {
 		sig_d = dff->getPort("\\D");
-- 
cgit v1.2.3