From f7363ac5086ccb8bdb97dcdbfed890c54e1ed153 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 2 Jan 2019 08:40:01 +0000 Subject: opt_lut: count eliminated cells, and set opt.did_something for them. --- passes/opt/opt_lut.cc | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 261af538f..8c564b0ed 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -36,7 +36,7 @@ struct OptLutWorker dict> luts_dlogics; dict> luts_dlogic_inputs; - int combined_count = 0; + int eliminated_count = 0, combined_count = 0; bool evaluate_lut(RTLIL::Cell *lut, dict inputs) { @@ -191,6 +191,12 @@ struct OptLutWorker log("Eliminating LUTs.\n"); for (auto lut : luts) { + if (limit == 0) + { + log("Limit reached.\n"); + break; + } + SigSpec lut_input = sigmap(lut->getPort("\\A")); pool &lut_dlogic_inputs = luts_dlogic_inputs[lut]; @@ -263,6 +269,10 @@ struct OptLutWorker luts_arity.erase(lut); luts_dlogics.erase(lut); luts_dlogic_inputs.erase(lut); + + eliminated_count++; + if (limit > 0) + limit--; } } } @@ -568,16 +578,20 @@ struct OptLutPass : public Pass { } extra_args(args, argidx, design); - int total_count = 0; + int eliminated_count = 0, combined_count = 0; for (auto module : design->selected_modules()) { - OptLutWorker worker(dlogic, module, limit - total_count); - total_count += worker.combined_count; + OptLutWorker worker(dlogic, module, limit - eliminated_count - combined_count); + eliminated_count += worker.eliminated_count; + combined_count += worker.combined_count; } - if (total_count) + if (eliminated_count) + design->scratchpad_set_bool("opt.did_something", true); + if (combined_count) design->scratchpad_set_bool("opt.did_something", true); log("\n"); - log("Combined %d LUTs.\n", total_count); + log("Eliminated %d LUTs.\n", eliminated_count); + log("Combined %d LUTs.\n", combined_count); } } OptLutPass; -- cgit v1.2.3 From 06143ab33f4064677586be2a2b0d763f0818e856 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 2 Jan 2019 09:36:32 +0000 Subject: opt_lut: use a worklist, and revisit cells affected by elimination. --- passes/opt/opt_lut.cc | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'passes/opt') diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 8c564b0ed..a79a9a2da 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -189,7 +189,8 @@ struct OptLutWorker log("\n"); log("Eliminating LUTs.\n"); - for (auto lut : luts) + pool worklist = luts; + while (worklist.size()) { if (limit == 0) { @@ -197,6 +198,7 @@ struct OptLutWorker break; } + auto lut = worklist.pop(); SigSpec lut_input = sigmap(lut->getPort("\\A")); pool &lut_dlogic_inputs = luts_dlogic_inputs[lut]; @@ -262,8 +264,13 @@ struct OptLutWorker else { SigSpec lut_output = lut->getPort("\\Y"); - module->connect(lut_output, value); + for (auto &port : index.query_ports(lut_output)) + { + if (port.cell != lut && luts.count(port.cell)) + worklist.insert(port.cell); + } + module->connect(lut_output, value); module->remove(lut); luts.erase(lut); luts_arity.erase(lut); @@ -280,7 +287,7 @@ struct OptLutWorker log("\n"); log("Combining LUTs.\n"); - pool worklist = luts; + worklist = luts; while (worklist.size()) { if (limit == 0) -- cgit v1.2.3 From c55dfb83693c6707ecb1d7dce7824a61e87eb44d Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 2 Jan 2019 10:21:58 +0000 Subject: opt_lut: reflect changes in sigmap. Otherwise, some LUTs will be missed during elimination. --- passes/opt/opt_lut.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes/opt') diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index a79a9a2da..b9a1ce7a7 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -271,6 +271,8 @@ struct OptLutWorker } module->connect(lut_output, value); + sigmap.add(lut_output, value); + module->remove(lut); luts.erase(lut); luts_arity.erase(lut); -- cgit v1.2.3