From 13f2f36884fa3e4a8329dab2556af7000cb085df Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Aug 2014 11:39:46 +0200
Subject: RIP $safe_pmux

---
 passes/opt/opt_muxtree.cc | 2 +-
 passes/opt/opt_reduce.cc  | 2 +-
 passes/opt/opt_share.cc   | 1 -
 3 files changed, 2 insertions(+), 3 deletions(-)

(limited to 'passes/opt')

diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 2660b33d4..daa063812 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -84,7 +84,7 @@ struct OptMuxtreeWorker
 		//	.const_activated
 		for (auto cell : module->cells())
 		{
-			if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
+			if (cell->type == "$mux" || cell->type == "$pmux")
 			{
 				RTLIL::SigSpec sig_a = cell->getPort("\\A");
 				RTLIL::SigSpec sig_b = cell->getPort("\\B");
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 5f3c4d29e..e2b4243d1 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -312,7 +312,7 @@ struct OptReduceWorker
 			std::vector<RTLIL::Cell*> cells;
 
 			for (auto &it : module->cells_)
-				if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second))
+				if ((it.second->type == "$mux" || it.second->type == "$pmux") && design->selected(module, it.second))
 					cells.push_back(it.second);
 
 			for (auto cell : cells)
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index eb970329d..e9a5e7fde 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -224,7 +224,6 @@ struct OptShareWorker
 		if (mode_nomux) {
 			ct.cell_types.erase("$mux");
 			ct.cell_types.erase("$pmux");
-			ct.cell_types.erase("$safe_pmux");
 		}
 
 		log("Finding identical cells in module `%s'.\n", module->name.c_str());
-- 
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