From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 10:18:00 +0200
Subject: Refactoring: Renamed RTLIL::Design::modules to modules_

---
 passes/opt/opt_reduce.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/opt/opt_reduce.cc')

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index d7de72353..b2b7cc8b9 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -367,7 +367,7 @@ struct OptReducePass : public Pass {
 		extra_args(args, argidx, design);
 
 		int total_count = 0;
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected(mod_it.second))
 				continue;
 			OptReduceWorker worker(design, mod_it.second, do_fine);
-- 
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