From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- passes/opt/opt_const.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/opt/opt_const.cc') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 672186006..290d4ffd9 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -45,7 +45,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) used_signals.add(sigmap(conn.second)); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (it.second->port_input) driven_signals.add(sigmap(it.second)); if (it.second->port_output) -- cgit v1.2.3