From 47f958ce4592a42e26f074c88063ac17c843ea71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Tue, 25 May 2021 01:55:44 +0200 Subject: memory_share: Add wide port support. --- passes/memory/memory_share.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'passes/memory') diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index d5a44f20c..98637720c 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -143,6 +143,7 @@ struct MemoryShareWorker bool cache_clk_enable = false; bool cache_clk_polarity = false; RTLIL::SigSpec cache_clk; + int cache_wide_log2 = 0; bool changed = false; @@ -152,12 +153,14 @@ struct MemoryShareWorker RTLIL::SigSpec addr = sigmap_xmux(port.addr); if (port.clk_enable != cache_clk_enable || + port.wide_log2 != cache_wide_log2 || (cache_clk_enable && (sigmap(port.clk) != cache_clk || port.clk_polarity != cache_clk_polarity))) { cache_clk_enable = port.clk_enable; cache_clk_polarity = port.clk_polarity; cache_clk = sigmap(port.clk); + cache_wide_log2 = port.wide_log2; last_port_by_addr.clear(); if (cache_clk_enable) @@ -290,18 +293,21 @@ struct MemoryShareWorker bool cache_clk_enable = false; bool cache_clk_polarity = false; RTLIL::SigSpec cache_clk; + int cache_wide_log2 = 0; for (int i = 0; i < GetSize(mem.wr_ports); i++) { auto &port = mem.wr_ports[i]; if (port.clk_enable != cache_clk_enable || + port.wide_log2 != cache_wide_log2 || (cache_clk_enable && (sigmap(port.clk) != cache_clk || port.clk_polarity != cache_clk_polarity))) { cache_clk_enable = port.clk_enable; cache_clk_polarity = port.clk_polarity; cache_clk = sigmap(port.clk); + cache_wide_log2 = port.wide_log2; } else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i)) considered_port_pairs.insert(i); -- cgit v1.2.3