From 7ad7f41bc555d7fc77a2201cdc485702505df637 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Mar 2020 12:21:40 -0700 Subject: kernel: share a single CellTypes within a pass --- passes/memory/memory_share.cc | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'passes/memory/memory_share.cc') diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index eb912cfd4..236c3c99c 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -665,9 +665,18 @@ struct MemoryShareWorker // Setup and run // ------------- - MemoryShareWorker(RTLIL::Design *design, RTLIL::Module *module) : - design(design), module(module), sigmap(module) + MemoryShareWorker(RTLIL::Design *design) : + design(design), modwalker(design) { + } + + void operator()(RTLIL::Module* module) + { + this->module = module; + sigmap.set(module); + sig_to_mux.clear(); + conditions_logic_cache.clear(); + std::map, std::vector>> memindex; sigmap_xmux = sigmap; @@ -717,7 +726,7 @@ struct MemoryShareWorker cone_ct.cell_types.erase("$shift"); cone_ct.cell_types.erase("$shiftx"); - modwalker.setup(design, module, &cone_ct); + modwalker.setup(module, &cone_ct); for (auto &it : memindex) consolidate_wr_using_sat(it.first, it.second.second); @@ -755,8 +764,11 @@ struct MemorySharePass : public Pass { void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n"); extra_args(args, 1, design); + + MemoryShareWorker msw(design); + for (auto module : design->selected_modules()) - MemoryShareWorker(design, module); + msw(module); } } MemorySharePass; -- cgit v1.2.3