From 3486235338faa1377bb4e1a8981a45b4ee6edfa9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 16:18:18 -0700
Subject: Make liberal use of IdString.in()

---
 passes/memory/memory_share.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'passes/memory/memory_share.cc')

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 172afe0cb..eb912cfd4 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -155,7 +155,7 @@ struct MemoryShareWorker
 		{
 			bool ignore_data_port = false;
 
-			if (cell->type == "$mux" || cell->type == "$pmux")
+			if (cell->type.in("$mux", "$pmux"))
 			{
 				std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
 				std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
@@ -173,7 +173,7 @@ struct MemoryShareWorker
 				continue;
 			}
 
-			if ((cell->type == "$memwr" || cell->type == "$memrd") &&
+			if (cell->type.in("$memwr", "$memrd") &&
 					cell->parameters.at("\\MEMID").decode_string() == memid)
 				ignore_data_port = true;
 
@@ -690,7 +690,7 @@ struct MemoryShareWorker
 					sigmap_xmux.add(cell->getPort("\\Y"), sig_a);
 			}
 
-			if (cell->type == "$mux" || cell->type == "$pmux")
+			if (cell->type.in("$mux", "$pmux"))
 			{
 				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
 				for (int i = 0; i < int(sig_y.size()); i++)
-- 
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