From 765f172211c8d7d8f14b6010193d8b53f5ec5e8f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Jul 2014 12:13:13 +0200 Subject: Changes to "memory" pass for new $memwr/$mem WR_EN interface --- passes/memory/memory_map.cc | 88 +++++++++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 35 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index e0e3802d1..10ab6e2f4 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -69,8 +69,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.width; i++) { - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i, 1); - if (wr_en.is_fully_const() && wr_en.as_int() == 0) { + RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); + if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } @@ -256,7 +256,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(j*mem_abits, mem_abits); RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j, 1); + RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width); RTLIL::Cell *c = new RTLIL::Cell; c->name = genid(cell->name, "$wreq", i, "", j); @@ -271,46 +271,64 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) module->cells[c->name] = c; count_wrmux++; - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$wreq", i, "", j, "$y"); - module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); + RTLIL::Wire *w_seladdr = new RTLIL::Wire; + w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y"); + module->wires[w_seladdr->name] = w_seladdr; + c->connections["\\Y"] = w_seladdr; - if (wr_en != RTLIL::SigSpec(1, 1)) + int wr_offset = 0; + while (wr_offset < wr_en.width) { + int wr_width = 1; + RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); + + while (wr_offset + wr_width < wr_en.width) { + RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); + if (next_wr_bit != wr_bit) + break; + wr_width++; + } + + RTLIL::Wire *w = w_seladdr; + + if (wr_bit != RTLIL::SigSpec(1, 1)) + { + c = new RTLIL::Cell; + c->name = genid(cell->name, "$wren", i, "", j, "", wr_offset); + c->type = "$and"; + c->parameters["\\A_SIGNED"] = RTLIL::Const(0); + c->parameters["\\B_SIGNED"] = RTLIL::Const(0); + c->parameters["\\A_WIDTH"] = RTLIL::Const(1); + c->parameters["\\B_WIDTH"] = RTLIL::Const(1); + c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + c->connections["\\A"] = w; + c->connections["\\B"] = wr_bit; + module->cells[c->name] = c; + + w = new RTLIL::Wire; + w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); + module->wires[w->name] = w; + c->connections["\\Y"] = RTLIL::SigSpec(w); + } + c = new RTLIL::Cell; - c->name = genid(cell->name, "$wren", i, "", j); - c->type = "$and"; - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = RTLIL::Const(1); - c->parameters["\\B_WIDTH"] = RTLIL::Const(1); - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = RTLIL::SigSpec(w); - c->connections["\\B"] = wr_en; + c->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset); + c->type = "$mux"; + c->parameters["\\WIDTH"] = wr_width; + c->connections["\\A"] = sig.extract(wr_offset, wr_width); + c->connections["\\B"] = wr_data.extract(wr_offset, wr_width); + c->connections["\\S"] = RTLIL::SigSpec(w); module->cells[c->name] = c; w = new RTLIL::Wire; - w->name = genid(cell->name, "$wren", i, "", j, "$y"); + w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); + w->width = wr_width; module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); - } + c->connections["\\Y"] = w; - c = new RTLIL::Cell; - c->name = genid(cell->name, "$wrmux", i, "", j); - c->type = "$mux"; - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->connections["\\A"] = sig; - c->connections["\\B"] = wr_data; - c->connections["\\S"] = RTLIL::SigSpec(w); - module->cells[c->name] = c; - - w = new RTLIL::Wire; - w->name = genid(cell->name, "$wrmux", i, "", j, "$y"); - w->width = mem_width; - module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); - sig = RTLIL::SigSpec(w); + sig.replace(wr_offset, w); + wr_offset += wr_width; + } } module->connections.push_back(RTLIL::SigSig(data_reg_in[i], sig)); -- cgit v1.2.3 From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 19:56:17 +0200 Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width --- passes/memory/memory_map.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 10ab6e2f4..b848e09e4 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -68,7 +68,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; - for (int i = 0; i < clocks.width; i++) { + for (int i = 0; i < clocks.__width; i++) { RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); @@ -89,7 +89,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) cell->name.c_str(), module->name.c_str(), i); return; } - if (refclock.width == 0) { + if (refclock.__width == 0) { refclock = clocks.extract(i, 1); refclock_pol = clocks_pol.bits[i]; } @@ -277,12 +277,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->connections["\\Y"] = w_seladdr; int wr_offset = 0; - while (wr_offset < wr_en.width) + while (wr_offset < wr_en.__width) { int wr_width = 1; RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); - while (wr_offset + wr_width < wr_en.width) { + while (wr_offset + wr_width < wr_en.__width) { RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); if (next_wr_bit != wr_bit) break; -- cgit v1.2.3 From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- passes/memory/memory_map.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index b848e09e4..e605e6e51 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -68,7 +68,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; - for (int i = 0; i < clocks.__width; i++) { + for (int i = 0; i < clocks.size(); i++) { RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); @@ -89,7 +89,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) cell->name.c_str(), module->name.c_str(), i); return; } - if (refclock.__width == 0) { + if (refclock.size() == 0) { refclock = clocks.extract(i, 1); refclock_pol = clocks_pol.bits[i]; } @@ -277,12 +277,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->connections["\\Y"] = w_seladdr; int wr_offset = 0; - while (wr_offset < wr_en.__width) + while (wr_offset < wr_en.size()) { int wr_width = 1; RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); - while (wr_offset + wr_width < wr_en.__width) { + while (wr_offset + wr_width < wr_en.size()) { RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); if (next_wr_bit != wr_bit) break; -- cgit v1.2.3 From 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 15:05:18 +0200 Subject: Use only module->addCell() and module->remove() to create and delete cells --- passes/memory/memory_map.cc | 42 +++++++++--------------------------------- 1 file changed, 9 insertions(+), 33 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index e605e6e51..b5f0520a4 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -57,8 +57,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) // delete unused memory cell if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { - module->cells.erase(cell->name); - delete cell; + module->remove(cell); return; } @@ -117,9 +116,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } else { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "", i); - c->type = "$dff"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; if (clocks_pol.bits.size() > 0) { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); @@ -128,7 +125,6 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); } - module->cells[c->name] = c; RTLIL::Wire *w_in = new RTLIL::Wire; w_in->name = genid(cell->name, "", i, "$d"); @@ -164,14 +160,11 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$rdreg", i); - c->type = "$dff"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); c->connections["\\D"] = rd_addr; - module->cells[c->name] = c; count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -184,14 +177,11 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } else { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$rdreg", i); - c->type = "$dff"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); c->connections["\\Q"] = rd_signals.back(); - module->cells[c->name] = c; count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -211,13 +201,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (size_t k = 0; k < rd_signals.size(); k++) { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$rdmux", i, "", j, "", k); - c->type = "$mux"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->connections["\\Y"] = rd_signals[k]; c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1); - module->cells[c->name] = c; count_mux++; RTLIL::Wire *w = new RTLIL::Wire; @@ -258,9 +245,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width); RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width); - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$wreq", i, "", j); - c->type = "$eq"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); c->parameters["\\B_SIGNED"] = RTLIL::Const(0); c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; @@ -268,7 +253,6 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits); c->connections["\\B"] = wr_addr; - module->cells[c->name] = c; count_wrmux++; RTLIL::Wire *w_seladdr = new RTLIL::Wire; @@ -293,9 +277,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) if (wr_bit != RTLIL::SigSpec(1, 1)) { - c = new RTLIL::Cell; - c->name = genid(cell->name, "$wren", i, "", j, "", wr_offset); - c->type = "$and"; + c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); c->parameters["\\B_SIGNED"] = RTLIL::Const(0); c->parameters["\\A_WIDTH"] = RTLIL::Const(1); @@ -303,7 +285,6 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); c->connections["\\A"] = w; c->connections["\\B"] = wr_bit; - module->cells[c->name] = c; w = new RTLIL::Wire; w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); @@ -311,14 +292,11 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->connections["\\Y"] = RTLIL::SigSpec(w); } - c = new RTLIL::Cell; - c->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset); - c->type = "$mux"; + c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; c->connections["\\A"] = sig.extract(wr_offset, wr_width); c->connections["\\B"] = wr_data.extract(wr_offset, wr_width); c->connections["\\S"] = RTLIL::SigSpec(w); - module->cells[c->name] = c; w = new RTLIL::Wire; w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); @@ -336,9 +314,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); - module->cells.erase(cell->name); - delete cell; - return; + module->remove(cell); } static void handle_module(RTLIL::Design *design, RTLIL::Module *module) -- cgit v1.2.3 From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- passes/memory/memory_map.cc | 74 ++++++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 37 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index b5f0520a4..a626b5aff 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -62,20 +62,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->connections["\\WR_CLK"]; + RTLIL::SigSpec clocks = cell->connections_["\\WR_CLK"]; RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(i*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(i*mem_width, mem_width); if (wr_addr.is_fully_const()) { // FIXME: Actually we should check for wr_en.is_fully_const() also and // create a $adff cell with this ports wr_en input as reset pin when wr_en @@ -120,10 +120,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; if (clocks_pol.bits.size() > 0) { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->connections["\\CLK"] = clocks.extract(0, 1); + c->connections_["\\CLK"] = clocks.extract(0, 1); } else { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); + c->connections_["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); } RTLIL::Wire *w_in = new RTLIL::Wire; @@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_in->width = mem_width; module->wires[w_in->name] = w_in; data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->connections["\\D"] = data_reg_in.back(); + c->connections_["\\D"] = data_reg_in.back(); RTLIL::Wire *w_out = new RTLIL::Wire; w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); @@ -141,7 +141,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_out->start_offset = mem_offset; module->wires[w_out->name] = w_out; data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->connections["\\Q"] = data_reg_out.back(); + c->connections_["\\Q"] = data_reg_out.back(); } } @@ -151,10 +151,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - RTLIL::SigSpec rd_addr = cell->connections["\\RD_ADDR"].extract(i*mem_abits, mem_abits); + RTLIL::SigSpec rd_addr = cell->connections_["\\RD_ADDR"].extract(i*mem_abits, mem_abits); std::vector rd_signals; - rd_signals.push_back(cell->connections["\\RD_DATA"].extract(i*mem_width, mem_width)); + rd_signals.push_back(cell->connections_["\\RD_DATA"].extract(i*mem_width, mem_width)); if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { @@ -163,8 +163,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); - c->connections["\\D"] = rd_addr; + c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); + c->connections_["\\D"] = rd_addr; count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -172,7 +172,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w->width = mem_abits; module->wires[w->name] = w; - c->connections["\\Q"] = RTLIL::SigSpec(w); + c->connections_["\\Q"] = RTLIL::SigSpec(w); rd_addr = RTLIL::SigSpec(w); } else @@ -180,8 +180,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); - c->connections["\\Q"] = rd_signals.back(); + c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); + c->connections_["\\Q"] = rd_signals.back(); count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -191,7 +191,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); - c->connections["\\D"] = rd_signals.back(); + c->connections_["\\D"] = rd_signals.back(); } } @@ -203,31 +203,31 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->connections["\\Y"] = rd_signals[k]; - c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1); + c->connections_["\\Y"] = rd_signals[k]; + c->connections_["\\S"] = rd_addr.extract(mem_abits-j-1, 1); count_mux++; RTLIL::Wire *w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a"); w->width = mem_width; module->wires[w->name] = w; - c->connections["\\A"] = RTLIL::SigSpec(w); + c->connections_["\\A"] = RTLIL::SigSpec(w); w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b"); w->width = mem_width; module->wires[w->name] = w; - c->connections["\\B"] = RTLIL::SigSpec(w); + c->connections_["\\B"] = RTLIL::SigSpec(w); - next_rd_signals.push_back(c->connections["\\A"]); - next_rd_signals.push_back(c->connections["\\B"]); + next_rd_signals.push_back(c->connections_["\\A"]); + next_rd_signals.push_back(c->connections_["\\B"]); } next_rd_signals.swap(rd_signals); } for (int j = 0; j < mem_size; j++) - module->connections.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); + module->connections_.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); } log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); @@ -241,9 +241,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) { - RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(j*mem_width, mem_width); RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); @@ -251,14 +251,14 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits); - c->connections["\\B"] = wr_addr; + c->connections_["\\A"] = RTLIL::SigSpec(i, mem_abits); + c->connections_["\\B"] = wr_addr; count_wrmux++; RTLIL::Wire *w_seladdr = new RTLIL::Wire; w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y"); module->wires[w_seladdr->name] = w_seladdr; - c->connections["\\Y"] = w_seladdr; + c->connections_["\\Y"] = w_seladdr; int wr_offset = 0; while (wr_offset < wr_en.size()) @@ -283,33 +283,33 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = w; - c->connections["\\B"] = wr_bit; + c->connections_["\\A"] = w; + c->connections_["\\B"] = wr_bit; w = new RTLIL::Wire; w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); + c->connections_["\\Y"] = RTLIL::SigSpec(w); } c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; - c->connections["\\A"] = sig.extract(wr_offset, wr_width); - c->connections["\\B"] = wr_data.extract(wr_offset, wr_width); - c->connections["\\S"] = RTLIL::SigSpec(w); + c->connections_["\\A"] = sig.extract(wr_offset, wr_width); + c->connections_["\\B"] = wr_data.extract(wr_offset, wr_width); + c->connections_["\\S"] = RTLIL::SigSpec(w); w = new RTLIL::Wire; w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); w->width = wr_width; module->wires[w->name] = w; - c->connections["\\Y"] = w; + c->connections_["\\Y"] = w; sig.replace(wr_offset, w); wr_offset += wr_width; } } - module->connections.push_back(RTLIL::SigSig(data_reg_in[i], sig)); + module->connections_.push_back(RTLIL::SigSig(data_reg_in[i], sig)); } log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); -- cgit v1.2.3 From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- passes/memory/memory_map.cc | 74 ++++++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 37 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index a626b5aff..5b180db62 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -62,20 +62,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->connections_["\\WR_CLK"]; + RTLIL::SigSpec clocks = cell->get("\\WR_CLK"); RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(i * mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(i*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(i*mem_width, mem_width); if (wr_addr.is_fully_const()) { // FIXME: Actually we should check for wr_en.is_fully_const() also and // create a $adff cell with this ports wr_en input as reset pin when wr_en @@ -120,10 +120,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; if (clocks_pol.bits.size() > 0) { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->connections_["\\CLK"] = clocks.extract(0, 1); + c->set("\\CLK", clocks.extract(0, 1)); } else { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->connections_["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); + c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); } RTLIL::Wire *w_in = new RTLIL::Wire; @@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_in->width = mem_width; module->wires[w_in->name] = w_in; data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->connections_["\\D"] = data_reg_in.back(); + c->set("\\D", data_reg_in.back()); RTLIL::Wire *w_out = new RTLIL::Wire; w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); @@ -141,7 +141,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_out->start_offset = mem_offset; module->wires[w_out->name] = w_out; data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->connections_["\\Q"] = data_reg_out.back(); + c->set("\\Q", data_reg_out.back()); } } @@ -151,10 +151,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - RTLIL::SigSpec rd_addr = cell->connections_["\\RD_ADDR"].extract(i*mem_abits, mem_abits); + RTLIL::SigSpec rd_addr = cell->get("\\RD_ADDR").extract(i*mem_abits, mem_abits); std::vector rd_signals; - rd_signals.push_back(cell->connections_["\\RD_DATA"].extract(i*mem_width, mem_width)); + rd_signals.push_back(cell->get("\\RD_DATA").extract(i*mem_width, mem_width)); if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { @@ -163,8 +163,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); - c->connections_["\\D"] = rd_addr; + c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1)); + c->set("\\D", rd_addr); count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -172,7 +172,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w->width = mem_abits; module->wires[w->name] = w; - c->connections_["\\Q"] = RTLIL::SigSpec(w); + c->set("\\Q", RTLIL::SigSpec(w)); rd_addr = RTLIL::SigSpec(w); } else @@ -180,8 +180,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); - c->connections_["\\Q"] = rd_signals.back(); + c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1)); + c->set("\\Q", rd_signals.back()); count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -191,7 +191,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); - c->connections_["\\D"] = rd_signals.back(); + c->set("\\D", rd_signals.back()); } } @@ -203,31 +203,31 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->connections_["\\Y"] = rd_signals[k]; - c->connections_["\\S"] = rd_addr.extract(mem_abits-j-1, 1); + c->set("\\Y", rd_signals[k]); + c->set("\\S", rd_addr.extract(mem_abits-j-1, 1)); count_mux++; RTLIL::Wire *w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a"); w->width = mem_width; module->wires[w->name] = w; - c->connections_["\\A"] = RTLIL::SigSpec(w); + c->set("\\A", RTLIL::SigSpec(w)); w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b"); w->width = mem_width; module->wires[w->name] = w; - c->connections_["\\B"] = RTLIL::SigSpec(w); + c->set("\\B", RTLIL::SigSpec(w)); - next_rd_signals.push_back(c->connections_["\\A"]); - next_rd_signals.push_back(c->connections_["\\B"]); + next_rd_signals.push_back(c->get("\\A")); + next_rd_signals.push_back(c->get("\\B")); } next_rd_signals.swap(rd_signals); } for (int j = 0; j < mem_size; j++) - module->connections_.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); + module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); } log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); @@ -241,9 +241,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) { - RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(j*mem_width, mem_width); RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); @@ -251,14 +251,14 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections_["\\A"] = RTLIL::SigSpec(i, mem_abits); - c->connections_["\\B"] = wr_addr; + c->set("\\A", RTLIL::SigSpec(i, mem_abits)); + c->set("\\B", wr_addr); count_wrmux++; RTLIL::Wire *w_seladdr = new RTLIL::Wire; w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y"); module->wires[w_seladdr->name] = w_seladdr; - c->connections_["\\Y"] = w_seladdr; + c->set("\\Y", w_seladdr); int wr_offset = 0; while (wr_offset < wr_en.size()) @@ -283,33 +283,33 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections_["\\A"] = w; - c->connections_["\\B"] = wr_bit; + c->set("\\A", w); + c->set("\\B", wr_bit); w = new RTLIL::Wire; w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); module->wires[w->name] = w; - c->connections_["\\Y"] = RTLIL::SigSpec(w); + c->set("\\Y", RTLIL::SigSpec(w)); } c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; - c->connections_["\\A"] = sig.extract(wr_offset, wr_width); - c->connections_["\\B"] = wr_data.extract(wr_offset, wr_width); - c->connections_["\\S"] = RTLIL::SigSpec(w); + c->set("\\A", sig.extract(wr_offset, wr_width)); + c->set("\\B", wr_data.extract(wr_offset, wr_width)); + c->set("\\S", RTLIL::SigSpec(w)); w = new RTLIL::Wire; w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); w->width = wr_width; module->wires[w->name] = w; - c->connections_["\\Y"] = w; + c->set("\\Y", w); sig.replace(wr_offset, w); wr_offset += wr_width; } } - module->connections_.push_back(RTLIL::SigSig(data_reg_in[i], sig)); + module->connect(RTLIL::SigSig(data_reg_in[i], sig)); } log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); -- cgit v1.2.3 From 946ddff9cef3ea0b4dad8664319fb13074133775 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 20:12:50 +0200 Subject: Changed a lot of code to the new RTLIL::Wire constructors --- passes/memory/memory_map.cc | 53 ++++++++++++--------------------------------- 1 file changed, 14 insertions(+), 39 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 5b180db62..32c7e63a0 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -126,20 +126,17 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); } - RTLIL::Wire *w_in = new RTLIL::Wire; - w_in->name = genid(cell->name, "", i, "$d"); - w_in->width = mem_width; - module->wires[w_in->name] = w_in; + RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); data_reg_in.push_back(RTLIL::SigSpec(w_in)); c->set("\\D", data_reg_in.back()); - RTLIL::Wire *w_out = new RTLIL::Wire; - w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); - if (module->wires.count(w_out->name) > 0) - w_out->name = genid(cell->name, "", i, "$q"); - w_out->width = mem_width; + std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); + if (module->wires.count(w_out_name) > 0) + w_out_name = genid(cell->name, "", i, "$q"); + + RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); w_out->start_offset = mem_offset; - module->wires[w_out->name] = w_out; + data_reg_out.push_back(RTLIL::SigSpec(w_out)); c->set("\\Q", data_reg_out.back()); } @@ -167,10 +164,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\D", rd_addr); count_dff++; - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdreg", i, "$q"); - w->width = mem_abits; - module->wires[w->name] = w; + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); c->set("\\Q", RTLIL::SigSpec(w)); rd_addr = RTLIL::SigSpec(w); @@ -184,10 +178,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\Q", rd_signals.back()); count_dff++; - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdreg", i, "$d"); - w->width = mem_width; - module->wires[w->name] = w; + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); @@ -207,17 +198,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\S", rd_addr.extract(mem_abits-j-1, 1)); count_mux++; - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a"); - w->width = mem_width; - module->wires[w->name] = w; - c->set("\\A", RTLIL::SigSpec(w)); - - w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b"); - w->width = mem_width; - module->wires[w->name] = w; - c->set("\\B", RTLIL::SigSpec(w)); + c->set("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->set("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); next_rd_signals.push_back(c->get("\\A")); next_rd_signals.push_back(c->get("\\B")); @@ -255,9 +237,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\B", wr_addr); count_wrmux++; - RTLIL::Wire *w_seladdr = new RTLIL::Wire; - w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y"); - module->wires[w_seladdr->name] = w_seladdr; + RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); c->set("\\Y", w_seladdr); int wr_offset = 0; @@ -286,9 +266,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\A", w); c->set("\\B", wr_bit); - w = new RTLIL::Wire; - w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); - module->wires[w->name] = w; + w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); c->set("\\Y", RTLIL::SigSpec(w)); } @@ -298,10 +276,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\B", wr_data.extract(wr_offset, wr_width)); c->set("\\S", RTLIL::SigSpec(w)); - w = new RTLIL::Wire; - w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); - w->width = wr_width; - module->wires[w->name] = w; + w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); c->set("\\Y", w); sig.replace(wr_offset, w); -- cgit v1.2.3 From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- passes/memory/memory_map.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 32c7e63a0..4f1666533 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\D", data_reg_in.back()); std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); - if (module->wires.count(w_out_name) > 0) + if (module->wires_.count(w_out_name) > 0) w_out_name = genid(cell->name, "", i, "$q"); RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); -- cgit v1.2.3 From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- passes/memory/memory_map.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 4f1666533..4bb0c8ccd 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -295,7 +295,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) static void handle_module(RTLIL::Design *design, RTLIL::Module *module) { std::vector cells; - for (auto &it : module->cells) + for (auto &it : module->cells_) if (it.second->type == "$mem" && design->selected(module, it.second)) cells.push_back(it.second); for (auto cell : cells) -- cgit v1.2.3 From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- passes/memory/memory_map.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 4bb0c8ccd..53394b19a 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -317,7 +317,7 @@ struct MemoryMapPass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } -- cgit v1.2.3 From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- passes/memory/memory_map.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 53394b19a..49291656c 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -22,7 +22,6 @@ #include #include #include -#include static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") { -- cgit v1.2.3 From 1cb25c05b37b0172dbc50e140fe20f25d973dd8a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 13:19:47 +0200 Subject: Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace --- passes/memory/memory_map.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 49291656c..0000bd507 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -41,7 +41,7 @@ static std::string genid(std::string name, std::string token1 = "", int i = -1, if (k >= 0) sstr << "[" << k << "]"; - sstr << token4 << "$" << (RTLIL::autoidx++); + sstr << token4 << "$" << (autoidx++); return sstr.str(); } -- cgit v1.2.3 From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 16:38:54 +0200 Subject: Renamed port access function on RTLIL::Cell, added param access functions --- passes/memory/memory_map.cc | 70 ++++++++++++++++++++++----------------------- 1 file changed, 35 insertions(+), 35 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 0000bd507..f1917b972 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -61,20 +61,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->get("\\WR_CLK"); + RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(i * mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(i*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); if (wr_addr.is_fully_const()) { // FIXME: Actually we should check for wr_en.is_fully_const() also and // create a $adff cell with this ports wr_en input as reset pin when wr_en @@ -119,15 +119,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; if (clocks_pol.bits.size() > 0) { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->set("\\CLK", clocks.extract(0, 1)); + c->setPort("\\CLK", clocks.extract(0, 1)); } else { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); + c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); } RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->set("\\D", data_reg_in.back()); + c->setPort("\\D", data_reg_in.back()); std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); if (module->wires_.count(w_out_name) > 0) @@ -137,7 +137,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_out->start_offset = mem_offset; data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->set("\\Q", data_reg_out.back()); + c->setPort("\\Q", data_reg_out.back()); } } @@ -147,10 +147,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - RTLIL::SigSpec rd_addr = cell->get("\\RD_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); std::vector rd_signals; - rd_signals.push_back(cell->get("\\RD_DATA").extract(i*mem_width, mem_width)); + rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { @@ -159,13 +159,13 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1)); - c->set("\\D", rd_addr); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\D", rd_addr); count_dff++; RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); - c->set("\\Q", RTLIL::SigSpec(w)); + c->setPort("\\Q", RTLIL::SigSpec(w)); rd_addr = RTLIL::SigSpec(w); } else @@ -173,15 +173,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1)); - c->set("\\Q", rd_signals.back()); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\Q", rd_signals.back()); count_dff++; RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); - c->set("\\D", rd_signals.back()); + c->setPort("\\D", rd_signals.back()); } } @@ -193,15 +193,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->set("\\Y", rd_signals[k]); - c->set("\\S", rd_addr.extract(mem_abits-j-1, 1)); + c->setPort("\\Y", rd_signals[k]); + c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); count_mux++; - c->set("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); - c->set("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); + c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - next_rd_signals.push_back(c->get("\\A")); - next_rd_signals.push_back(c->get("\\B")); + next_rd_signals.push_back(c->getPort("\\A")); + next_rd_signals.push_back(c->getPort("\\B")); } next_rd_signals.swap(rd_signals); @@ -222,9 +222,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) { - RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); @@ -232,12 +232,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->set("\\A", RTLIL::SigSpec(i, mem_abits)); - c->set("\\B", wr_addr); + c->setPort("\\A", RTLIL::SigSpec(i, mem_abits)); + c->setPort("\\B", wr_addr); count_wrmux++; RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); - c->set("\\Y", w_seladdr); + c->setPort("\\Y", w_seladdr); int wr_offset = 0; while (wr_offset < wr_en.size()) @@ -262,21 +262,21 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->set("\\A", w); - c->set("\\B", wr_bit); + c->setPort("\\A", w); + c->setPort("\\B", wr_bit); w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); - c->set("\\Y", RTLIL::SigSpec(w)); + c->setPort("\\Y", RTLIL::SigSpec(w)); } c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; - c->set("\\A", sig.extract(wr_offset, wr_width)); - c->set("\\B", wr_data.extract(wr_offset, wr_width)); - c->set("\\S", RTLIL::SigSpec(w)); + c->setPort("\\A", sig.extract(wr_offset, wr_width)); + c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); + c->setPort("\\S", RTLIL::SigSpec(w)); w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); - c->set("\\Y", w); + c->setPort("\\Y", w); sig.replace(wr_offset, w); wr_offset += wr_width; -- cgit v1.2.3 From b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 13:11:01 +0200 Subject: More cleanups related to RTLIL::IdString usage --- passes/memory/memory_map.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index f1917b972..8dc66f2cd 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -23,10 +23,10 @@ #include #include -static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") +static std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") { std::stringstream sstr; - sstr << "$memory" << name << token1; + sstr << "$memory" << name.str() << token1; if (i >= 0) sstr << "[" << i << "]"; -- cgit v1.2.3 From 66763fad4e3f93b11fbc72acd94174a56084ad17 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 17:39:08 +0200 Subject: Using worker class in memory_map --- passes/memory/memory_map.cc | 457 ++++++++++++++++++++++---------------------- 1 file changed, 231 insertions(+), 226 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 8dc66f2cd..878994679 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -23,283 +23,289 @@ #include #include -static std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") +struct MemoryMapWorker { - std::stringstream sstr; - sstr << "$memory" << name.str() << token1; - - if (i >= 0) - sstr << "[" << i << "]"; + RTLIL::Design *design; + RTLIL::Module *module; - sstr << token2; + std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") + { + std::stringstream sstr; + sstr << "$memory" << name.str() << token1; + + if (i >= 0) + sstr << "[" << i << "]"; - if (j >= 0) - sstr << "[" << j << "]"; + sstr << token2; - sstr << token3; + if (j >= 0) + sstr << "[" << j << "]"; - if (k >= 0) - sstr << "[" << k << "]"; + sstr << token3; - sstr << token4 << "$" << (autoidx++); - return sstr.str(); -} + if (k >= 0) + sstr << "[" << k << "]"; -static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) -{ - std::set static_ports; - std::map static_cells_map; - int mem_size = cell->parameters["\\SIZE"].as_int(); - int mem_width = cell->parameters["\\WIDTH"].as_int(); - int mem_offset = cell->parameters["\\OFFSET"].as_int(); - int mem_abits = cell->parameters["\\ABITS"].as_int(); - - // delete unused memory cell - if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { - module->remove(cell); - return; + sstr << token4 << "$" << (autoidx++); + return sstr.str(); } - // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); - RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; - RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; - RTLIL::SigSpec refclock; - RTLIL::State refclock_pol = RTLIL::State::Sx; - for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); - if (wr_en.is_fully_const() && !wr_en.as_bool()) { - static_ports.insert(i); - continue; + void handle_cell(RTLIL::Cell *cell) + { + std::set static_ports; + std::map static_cells_map; + int mem_size = cell->parameters["\\SIZE"].as_int(); + int mem_width = cell->parameters["\\WIDTH"].as_int(); + int mem_offset = cell->parameters["\\OFFSET"].as_int(); + int mem_abits = cell->parameters["\\ABITS"].as_int(); + + // delete unused memory cell + if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { + module->remove(cell); + return; } - if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); - if (wr_addr.is_fully_const()) { - // FIXME: Actually we should check for wr_en.is_fully_const() also and - // create a $adff cell with this ports wr_en input as reset pin when wr_en - // is not a simple static 1. - static_cells_map[wr_addr.as_int()] = wr_data; + + // all write ports must share the same clock + RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); + RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; + RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; + RTLIL::SigSpec refclock; + RTLIL::State refclock_pol = RTLIL::State::Sx; + for (int i = 0; i < clocks.size(); i++) { + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); + if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } - log("Not mapping memory cell %s in module %s (write port %d has no clock).\n", - cell->name.c_str(), module->name.c_str(), i); - return; - } - if (refclock.size() == 0) { - refclock = clocks.extract(i, 1); - refclock_pol = clocks_pol.bits[i]; - } - if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) { - log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n", - cell->name.c_str(), module->name.c_str(), i); - return; + if (clocks_en.bits[i] != RTLIL::State::S1) { + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); + if (wr_addr.is_fully_const()) { + // FIXME: Actually we should check for wr_en.is_fully_const() also and + // create a $adff cell with this ports wr_en input as reset pin when wr_en + // is not a simple static 1. + static_cells_map[wr_addr.as_int()] = wr_data; + static_ports.insert(i); + continue; + } + log("Not mapping memory cell %s in module %s (write port %d has no clock).\n", + cell->name.c_str(), module->name.c_str(), i); + return; + } + if (refclock.size() == 0) { + refclock = clocks.extract(i, 1); + refclock_pol = clocks_pol.bits[i]; + } + if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) { + log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n", + cell->name.c_str(), module->name.c_str(), i); + return; + } } - } - log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str()); + log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str()); - std::vector data_reg_in; - std::vector data_reg_out; + std::vector data_reg_in; + std::vector data_reg_out; - int count_static = 0; + int count_static = 0; - for (int i = 0; i < mem_size; i++) - { - if (static_cells_map.count(i) > 0) + for (int i = 0; i < mem_size; i++) { - data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width)); - data_reg_out.push_back(static_cells_map[i]); - count_static++; - } - else - { - RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - if (clocks_pol.bits.size() > 0) { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->setPort("\\CLK", clocks.extract(0, 1)); - } else { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); + if (static_cells_map.count(i) > 0) + { + data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width)); + data_reg_out.push_back(static_cells_map[i]); + count_static++; } + else + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); + c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + if (clocks_pol.bits.size() > 0) { + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); + c->setPort("\\CLK", clocks.extract(0, 1)); + } else { + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); + c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); + } - RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); - data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->setPort("\\D", data_reg_in.back()); + RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); + data_reg_in.push_back(RTLIL::SigSpec(w_in)); + c->setPort("\\D", data_reg_in.back()); - std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); - if (module->wires_.count(w_out_name) > 0) - w_out_name = genid(cell->name, "", i, "$q"); + std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); + if (module->wires_.count(w_out_name) > 0) + w_out_name = genid(cell->name, "", i, "$q"); - RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); - w_out->start_offset = mem_offset; + RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); + w_out->start_offset = mem_offset; - data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->setPort("\\Q", data_reg_out.back()); + data_reg_out.push_back(RTLIL::SigSpec(w_out)); + c->setPort("\\Q", data_reg_out.back()); + } } - } - - log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width); - int count_dff = 0, count_mux = 0, count_wrmux = 0; - - for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) - { - RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); + log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width); - std::vector rd_signals; - rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); + int count_dff = 0, count_mux = 0, count_wrmux = 0; - if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) + for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) - { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); - c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); - c->setPort("\\D", rd_addr); - count_dff++; + RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); - RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); + std::vector rd_signals; + rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); - c->setPort("\\Q", RTLIL::SigSpec(w)); - rd_addr = RTLIL::SigSpec(w); - } - else + if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); - c->setPort("\\Q", rd_signals.back()); - count_dff++; + if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); + c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\D", rd_addr); + count_dff++; - RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); - rd_signals.clear(); - rd_signals.push_back(RTLIL::SigSpec(w)); - c->setPort("\\D", rd_signals.back()); + c->setPort("\\Q", RTLIL::SigSpec(w)); + rd_addr = RTLIL::SigSpec(w); + } + else + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); + c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\Q", rd_signals.back()); + count_dff++; + + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); + + rd_signals.clear(); + rd_signals.push_back(RTLIL::SigSpec(w)); + c->setPort("\\D", rd_signals.back()); + } } - } - - for (int j = 0; j < mem_abits; j++) - { - std::vector next_rd_signals; - for (size_t k = 0; k < rd_signals.size(); k++) + for (int j = 0; j < mem_abits; j++) { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->setPort("\\Y", rd_signals[k]); - c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); - count_mux++; + std::vector next_rd_signals; - c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); - c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - - next_rd_signals.push_back(c->getPort("\\A")); - next_rd_signals.push_back(c->getPort("\\B")); - } + for (size_t k = 0; k < rd_signals.size(); k++) + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); + c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + c->setPort("\\Y", rd_signals[k]); + c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); + count_mux++; - next_rd_signals.swap(rd_signals); - } + c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - for (int j = 0; j < mem_size; j++) - module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); - } + next_rd_signals.push_back(c->getPort("\\A")); + next_rd_signals.push_back(c->getPort("\\B")); + } - log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); + next_rd_signals.swap(rd_signals); + } - for (int i = 0; i < mem_size; i++) - { - if (static_cells_map.count(i) > 0) - continue; + for (int j = 0; j < mem_size; j++) + module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); + } - RTLIL::SigSpec sig = data_reg_out[i]; + log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); - for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) + for (int i = 0; i < mem_size; i++) { - RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); - - RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->setPort("\\A", RTLIL::SigSpec(i, mem_abits)); - c->setPort("\\B", wr_addr); - count_wrmux++; - - RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); - c->setPort("\\Y", w_seladdr); - - int wr_offset = 0; - while (wr_offset < wr_en.size()) - { - int wr_width = 1; - RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); - - while (wr_offset + wr_width < wr_en.size()) { - RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); - if (next_wr_bit != wr_bit) - break; - wr_width++; - } + if (static_cells_map.count(i) > 0) + continue; - RTLIL::Wire *w = w_seladdr; + RTLIL::SigSpec sig = data_reg_out[i]; - if (wr_bit != RTLIL::SigSpec(1, 1)) + for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) + { + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); + + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); + c->parameters["\\A_SIGNED"] = RTLIL::Const(0); + c->parameters["\\B_SIGNED"] = RTLIL::Const(0); + c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; + c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; + c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + c->setPort("\\A", RTLIL::SigSpec(i, mem_abits)); + c->setPort("\\B", wr_addr); + count_wrmux++; + + RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); + c->setPort("\\Y", w_seladdr); + + int wr_offset = 0; + while (wr_offset < wr_en.size()) { - c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = RTLIL::Const(1); - c->parameters["\\B_WIDTH"] = RTLIL::Const(1); - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->setPort("\\A", w); - c->setPort("\\B", wr_bit); - - w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); - c->setPort("\\Y", RTLIL::SigSpec(w)); + int wr_width = 1; + RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); + + while (wr_offset + wr_width < wr_en.size()) { + RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); + if (next_wr_bit != wr_bit) + break; + wr_width++; + } + + RTLIL::Wire *w = w_seladdr; + + if (wr_bit != RTLIL::SigSpec(1, 1)) + { + c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); + c->parameters["\\A_SIGNED"] = RTLIL::Const(0); + c->parameters["\\B_SIGNED"] = RTLIL::Const(0); + c->parameters["\\A_WIDTH"] = RTLIL::Const(1); + c->parameters["\\B_WIDTH"] = RTLIL::Const(1); + c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + c->setPort("\\A", w); + c->setPort("\\B", wr_bit); + + w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); + c->setPort("\\Y", RTLIL::SigSpec(w)); + } + + c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); + c->parameters["\\WIDTH"] = wr_width; + c->setPort("\\A", sig.extract(wr_offset, wr_width)); + c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); + c->setPort("\\S", RTLIL::SigSpec(w)); + + w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); + c->setPort("\\Y", w); + + sig.replace(wr_offset, w); + wr_offset += wr_width; } - - c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); - c->parameters["\\WIDTH"] = wr_width; - c->setPort("\\A", sig.extract(wr_offset, wr_width)); - c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); - c->setPort("\\S", RTLIL::SigSpec(w)); - - w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); - c->setPort("\\Y", w); - - sig.replace(wr_offset, w); - wr_offset += wr_width; } - } - module->connect(RTLIL::SigSig(data_reg_in[i], sig)); - } + module->connect(RTLIL::SigSig(data_reg_in[i], sig)); + } - log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); + log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); - module->remove(cell); -} + module->remove(cell); + } -static void handle_module(RTLIL::Design *design, RTLIL::Module *module) -{ - std::vector cells; - for (auto &it : module->cells_) - if (it.second->type == "$mem" && design->selected(module, it.second)) - cells.push_back(it.second); - for (auto cell : cells) - handle_cell(module, cell); -} + MemoryMapWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module) + { + std::vector cells; + for (auto cell : module->selected_cells()) + if (cell->type == "$mem" && design->selected(module, cell)) + cells.push_back(cell); + for (auto cell : cells) + handle_cell(cell); + } +}; struct MemoryMapPass : public Pass { MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { } @@ -316,9 +322,8 @@ struct MemoryMapPass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - handle_module(design, mod_it.second); + for (auto mod : design->selected_modules()) + MemoryMapWorker(design, mod); } } MemoryMapPass; -- cgit v1.2.3 From 6ff46323a30d710a9518cffb8c2ae9a5621b7bfc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 18:18:15 +0200 Subject: Improved write address decoder generation memory_map --- passes/memory/memory_map.cc | 44 ++++++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 16 deletions(-) (limited to 'passes/memory/memory_map.cc') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 878994679..eecb6f35d 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -28,6 +28,8 @@ struct MemoryMapWorker RTLIL::Design *design; RTLIL::Module *module; + std::map, RTLIL::SigBit> decoder_cache; + std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") { std::stringstream sstr; @@ -50,6 +52,27 @@ struct MemoryMapWorker return sstr.str(); } + RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val) + { + std::pair key(addr_sig, addr_val); + log_assert(SIZE(addr_sig) == SIZE(addr_val)); + + if (decoder_cache.count(key) == 0) { + if (SIZE(addr_sig) < 2) { + decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val); + } else { + int split_at = SIZE(addr_sig) / 2; + RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at)); + RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, SIZE(addr_sig) - split_at), addr_val.extract(split_at, SIZE(addr_val) - split_at)); + decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq); + } + } + + RTLIL::SigBit bit = decoder_cache.at(key); + log_assert(bit.wire != nullptr && SIZE(bit.wire) == 1); + return bit.wire; + } + void handle_cell(RTLIL::Cell *cell) { std::set static_ports; @@ -230,19 +253,7 @@ struct MemoryMapWorker RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); - - RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->setPort("\\A", RTLIL::SigSpec(i, mem_abits)); - c->setPort("\\B", wr_addr); - count_wrmux++; - - RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); - c->setPort("\\Y", w_seladdr); + RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(i, mem_abits)); int wr_offset = 0; while (wr_offset < wr_en.size()) @@ -261,7 +272,7 @@ struct MemoryMapWorker if (wr_bit != RTLIL::SigSpec(1, 1)) { - c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); c->parameters["\\B_SIGNED"] = RTLIL::Const(0); c->parameters["\\A_WIDTH"] = RTLIL::Const(1); @@ -274,7 +285,7 @@ struct MemoryMapWorker c->setPort("\\Y", RTLIL::SigSpec(w)); } - c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; c->setPort("\\A", sig.extract(wr_offset, wr_width)); c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); @@ -285,13 +296,14 @@ struct MemoryMapWorker sig.replace(wr_offset, w); wr_offset += wr_width; + count_wrmux++; } } module->connect(RTLIL::SigSig(data_reg_in[i], sig)); } - log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); + log(" write interface: %d write mux blocks.\n", count_wrmux); module->remove(cell); } -- cgit v1.2.3