From 68c99bf7349cf56385ee803144dd7d8e219be8d5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 1 Jun 2014 11:32:27 +0200
Subject: Fixed log messages in memory_dff

---
 passes/memory/memory_dff.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 2502a8b61..e8da6d642 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -111,6 +111,8 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		log("merged $dff to cell.\n");
 	}
+
+	log("no (compatible) $dff found.\n");
 }
 
 static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
-- 
cgit v1.2.3


From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 19:56:17 +0200
Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width

---
 passes/memory/memory_dff.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index e8da6d642..174417bd6 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -34,9 +34,9 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 	normalize_sig(module, sig);
 	sig.expand();
 
-	for (size_t i = 0; i < sig.chunks.size(); i++)
+	for (size_t i = 0; i < sig.__chunks.size(); i++)
 	{
-		RTLIL::SigChunk &chunk = sig.chunks[i];
+		RTLIL::SigChunk &chunk = sig.__chunks[i];
 
 		if (chunk.wire == NULL)
 			continue;
@@ -59,11 +59,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 			normalize_sig(module, q_norm);
 
 			RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]);
-			if (d.width != 1)
+			if (d.__width != 1)
 				continue;
 
-			assert(d.chunks.size() == 1);
-			chunk = d.chunks[0];
+			assert(d.__chunks.size() == 1);
+			chunk = d.__chunks[0];
 			clk = cell->connections["\\CLK"];
 			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 			goto replaced_this_bit;
@@ -125,7 +125,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	RTLIL::Wire *wire = new RTLIL::Wire;
 	wire->name = sstr.str();
-	wire->width = sig.width;
+	wire->width = sig.__width;
 	module->wires[wire->name] = wire;
 
 	RTLIL::SigSpec newsig(wire);
-- 
cgit v1.2.3


From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 20:15:14 +0200
Subject: SigSpec refactoring: using the accessor functions everywhere

---
 passes/memory/memory_dff.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 174417bd6..8bae24cff 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -34,9 +34,9 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 	normalize_sig(module, sig);
 	sig.expand();
 
-	for (size_t i = 0; i < sig.__chunks.size(); i++)
+	for (size_t i = 0; i < sig.chunks().size(); i++)
 	{
-		RTLIL::SigChunk &chunk = sig.__chunks[i];
+		RTLIL::SigChunk &chunk = sig.chunks()[i];
 
 		if (chunk.wire == NULL)
 			continue;
@@ -59,11 +59,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 			normalize_sig(module, q_norm);
 
 			RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]);
-			if (d.__width != 1)
+			if (d.size() != 1)
 				continue;
 
-			assert(d.__chunks.size() == 1);
-			chunk = d.__chunks[0];
+			assert(d.chunks().size() == 1);
+			chunk = d.chunks()[0];
 			clk = cell->connections["\\CLK"];
 			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 			goto replaced_this_bit;
@@ -125,7 +125,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	RTLIL::Wire *wire = new RTLIL::Wire;
 	wire->name = sstr.str();
-	wire->width = sig.__width;
+	wire->width = sig.size();
 	module->wires[wire->name] = wire;
 
 	RTLIL::SigSpec newsig(wire);
-- 
cgit v1.2.3


From 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 22 Jul 2014 20:58:44 +0200
Subject: SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only,
 created interim RTLIL::SigSpec::chunks_rw()

---
 passes/memory/memory_dff.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 8bae24cff..dee48597f 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -36,7 +36,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 
 	for (size_t i = 0; i < sig.chunks().size(); i++)
 	{
-		RTLIL::SigChunk &chunk = sig.chunks()[i];
+		RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
 
 		if (chunk.wire == NULL)
 			continue;
-- 
cgit v1.2.3


From 4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 23 Jul 2014 15:36:09 +0200
Subject: Fixed all users of SigSpec::chunks_rw() and removed it

---
 passes/memory/memory_dff.cc | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index dee48597f..b1f1e22b5 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -32,13 +32,10 @@ static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
 static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
 {
 	normalize_sig(module, sig);
-	sig.expand();
 
-	for (size_t i = 0; i < sig.chunks().size(); i++)
+	for (auto &bit : sig)
 	{
-		RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
-
-		if (chunk.wire == NULL)
+		if (bit.wire == NULL)
 			continue;
 
 		for (auto &cell_it : module->cells)
@@ -58,12 +55,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 			RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"];
 			normalize_sig(module, q_norm);
 
-			RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]);
+			RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections[after ? "\\Q" : "\\D"]);
 			if (d.size() != 1)
 				continue;
 
-			assert(d.chunks().size() == 1);
-			chunk = d.chunks()[0];
+			bit = d;
 			clk = cell->connections["\\CLK"];
 			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 			goto replaced_this_bit;
-- 
cgit v1.2.3


From c094c53de83707a5bf1b268640283f1dde235873 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 23 Jul 2014 20:32:28 +0200
Subject: Removed RTLIL::SigSpec::optimize()

---
 passes/memory/memory_dff.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index b1f1e22b5..56915776e 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -69,7 +69,6 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 	replaced_this_bit:;
 	}
 
-	sig.optimize();
 	return true;
 }
 
-- 
cgit v1.2.3


From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 11:58:03 +0200
Subject: Renamed RTLIL::{Module,Cell}::connections to connections_

---
 passes/memory/memory_dff.cc | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 56915776e..63f7d0527 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -25,7 +25,7 @@
 
 static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
 {
-	for (auto &conn : module->connections)
+	for (auto &conn : module->connections_)
 		sig.replace(conn.first, conn.second);
 }
 
@@ -46,21 +46,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 				continue;
 
 			if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-				if (cell->connections["\\CLK"] != clk)
+				if (cell->connections_["\\CLK"] != clk)
 					continue;
 				if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
 					continue;
 			}
 
-			RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"];
+			RTLIL::SigSpec q_norm = cell->connections_[after ? "\\D" : "\\Q"];
 			normalize_sig(module, q_norm);
 
-			RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections[after ? "\\Q" : "\\D"]);
+			RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections_[after ? "\\Q" : "\\D"]);
 			if (d.size() != 1)
 				continue;
 
 			bit = d;
-			clk = cell->connections["\\CLK"];
+			clk = cell->connections_["\\CLK"];
 			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 			goto replaced_this_bit;
 		}
@@ -79,29 +79,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
 	bool clk_polarity = 0;
 
-	RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"];
+	RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"];
 	if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
 		log("no (compatible) $dff for address input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_data = cell->connections["\\DATA"];
+	RTLIL::SigSpec sig_data = cell->connections_["\\DATA"];
 	if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
 		log("no (compatible) $dff for data input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_en = cell->connections["\\EN"];
+	RTLIL::SigSpec sig_en = cell->connections_["\\EN"];
 	if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
 		log("no (compatible) $dff for enable input found.\n");
 		return;
 	}
 
 	if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-		cell->connections["\\CLK"] = clk;
-		cell->connections["\\ADDR"] = sig_addr;
-		cell->connections["\\DATA"] = sig_data;
-		cell->connections["\\EN"] = sig_en;
+		cell->connections_["\\CLK"] = clk;
+		cell->connections_["\\ADDR"] = sig_addr;
+		cell->connections_["\\DATA"] = sig_data;
+		cell->connections_["\\EN"] = sig_en;
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		log("merged $dff to cell.\n");
@@ -128,7 +128,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 	for (auto &cell_it : module->cells) {
 		RTLIL::Cell *cell = cell_it.second;
 		if (cell->type == "$dff")
-			cell->connections["\\Q"].replace(sig, newsig);
+			cell->connections_["\\Q"].replace(sig, newsig);
 	}
 }
 
@@ -139,13 +139,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	bool clk_polarity = 0;
 
 	RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_data = cell->connections["\\DATA"];
+	RTLIL::SigSpec sig_data = cell->connections_["\\DATA"];
 	if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) &&
 			clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
 		disconnect_dff(module, sig_data);
-		cell->connections["\\CLK"] = clk_data;
-		cell->connections["\\DATA"] = sig_data;
+		cell->connections_["\\CLK"] = clk_data;
+		cell->connections_["\\DATA"] = sig_data;
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
@@ -154,12 +154,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"];
+	RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"];
 	if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) &&
 			clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
-		cell->connections["\\CLK"] = clk_addr;
-		cell->connections["\\ADDR"] = sig_addr;
+		cell->connections_["\\CLK"] = clk_addr;
+		cell->connections_["\\ADDR"] = sig_addr;
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
-- 
cgit v1.2.3


From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 14:32:50 +0200
Subject: Changed users of cell->connections_ to the new API (sed command)

git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
---
 passes/memory/memory_dff.cc | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 63f7d0527..0513aa3d2 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -25,7 +25,7 @@
 
 static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
 {
-	for (auto &conn : module->connections_)
+	for (auto &conn : module->connections())
 		sig.replace(conn.first, conn.second);
 }
 
@@ -46,21 +46,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 				continue;
 
 			if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-				if (cell->connections_["\\CLK"] != clk)
+				if (cell->get("\\CLK") != clk)
 					continue;
 				if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
 					continue;
 			}
 
-			RTLIL::SigSpec q_norm = cell->connections_[after ? "\\D" : "\\Q"];
+			RTLIL::SigSpec q_norm = cell->connections()[after ? "\\D" : "\\Q"];
 			normalize_sig(module, q_norm);
 
-			RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections_[after ? "\\Q" : "\\D"]);
+			RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections()[after ? "\\Q" : "\\D"]);
 			if (d.size() != 1)
 				continue;
 
 			bit = d;
-			clk = cell->connections_["\\CLK"];
+			clk = cell->get("\\CLK");
 			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 			goto replaced_this_bit;
 		}
@@ -79,29 +79,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
 	bool clk_polarity = 0;
 
-	RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"];
+	RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
 	if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
 		log("no (compatible) $dff for address input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_data = cell->connections_["\\DATA"];
+	RTLIL::SigSpec sig_data = cell->get("\\DATA");
 	if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
 		log("no (compatible) $dff for data input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_en = cell->connections_["\\EN"];
+	RTLIL::SigSpec sig_en = cell->get("\\EN");
 	if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
 		log("no (compatible) $dff for enable input found.\n");
 		return;
 	}
 
 	if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-		cell->connections_["\\CLK"] = clk;
-		cell->connections_["\\ADDR"] = sig_addr;
-		cell->connections_["\\DATA"] = sig_data;
-		cell->connections_["\\EN"] = sig_en;
+		cell->set("\\CLK", clk);
+		cell->set("\\ADDR", sig_addr);
+		cell->set("\\DATA", sig_data);
+		cell->set("\\EN", sig_en);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		log("merged $dff to cell.\n");
@@ -128,7 +128,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 	for (auto &cell_it : module->cells) {
 		RTLIL::Cell *cell = cell_it.second;
 		if (cell->type == "$dff")
-			cell->connections_["\\Q"].replace(sig, newsig);
+			cell->get("\\Q").replace(sig, newsig);
 	}
 }
 
@@ -139,13 +139,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	bool clk_polarity = 0;
 
 	RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_data = cell->connections_["\\DATA"];
+	RTLIL::SigSpec sig_data = cell->get("\\DATA");
 	if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) &&
 			clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
 		disconnect_dff(module, sig_data);
-		cell->connections_["\\CLK"] = clk_data;
-		cell->connections_["\\DATA"] = sig_data;
+		cell->set("\\CLK", clk_data);
+		cell->set("\\DATA", sig_data);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
@@ -154,12 +154,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"];
+	RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
 	if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) &&
 			clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
-		cell->connections_["\\CLK"] = clk_addr;
-		cell->connections_["\\ADDR"] = sig_addr;
+		cell->set("\\CLK", clk_addr);
+		cell->set("\\ADDR", sig_addr);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
-- 
cgit v1.2.3


From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 15:57:57 +0200
Subject: Manual fixes for new cell connections API

---
 passes/memory/memory_dff.cc | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 0513aa3d2..999c969b5 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -52,10 +52,10 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 					continue;
 			}
 
-			RTLIL::SigSpec q_norm = cell->connections()[after ? "\\D" : "\\Q"];
+			RTLIL::SigSpec q_norm = cell->get(after ? "\\D" : "\\Q");
 			normalize_sig(module, q_norm);
 
-			RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections()[after ? "\\Q" : "\\D"]);
+			RTLIL::SigSpec d = q_norm.extract(bit, &cell->get(after ? "\\Q" : "\\D"));
 			if (d.size() != 1)
 				continue;
 
@@ -127,8 +127,11 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	for (auto &cell_it : module->cells) {
 		RTLIL::Cell *cell = cell_it.second;
-		if (cell->type == "$dff")
-			cell->get("\\Q").replace(sig, newsig);
+		if (cell->type == "$dff") {
+			RTLIL::SigSpec new_q = cell->get("\\Q");
+			new_q.replace(sig, newsig);
+			cell->set("\\Q", new_q);
+		}
 	}
 }
 
-- 
cgit v1.2.3


From 946ddff9cef3ea0b4dad8664319fb13074133775 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 20:12:50 +0200
Subject: Changed a lot of code to the new RTLIL::Wire constructors

---
 passes/memory/memory_dff.cc | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 999c969b5..b63b3aec6 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -118,18 +118,13 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 	std::stringstream sstr;
 	sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++);
 
-	RTLIL::Wire *wire = new RTLIL::Wire;
-	wire->name = sstr.str();
-	wire->width = sig.size();
-	module->wires[wire->name] = wire;
-
-	RTLIL::SigSpec newsig(wire);
+	RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
 
 	for (auto &cell_it : module->cells) {
 		RTLIL::Cell *cell = cell_it.second;
 		if (cell->type == "$dff") {
 			RTLIL::SigSpec new_q = cell->get("\\Q");
-			new_q.replace(sig, newsig);
+			new_q.replace(sig, new_sig);
 			cell->set("\\Q", new_q);
 		}
 	}
-- 
cgit v1.2.3


From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 01:51:45 +0200
Subject: Refactoring: Renamed RTLIL::Module::cells to cells_

---
 passes/memory/memory_dff.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index b63b3aec6..bb8b052dc 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -38,7 +38,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 		if (bit.wire == NULL)
 			continue;
 
-		for (auto &cell_it : module->cells)
+		for (auto &cell_it : module->cells_)
 		{
 			RTLIL::Cell *cell = cell_it.second;
 
@@ -120,7 +120,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
 
-	for (auto &cell_it : module->cells) {
+	for (auto &cell_it : module->cells_) {
 		RTLIL::Cell *cell = cell_it.second;
 		if (cell->type == "$dff") {
 			RTLIL::SigSpec new_q = cell->get("\\Q");
@@ -170,7 +170,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 
 static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only)
 {
-	for (auto &cell_it : module->cells) {
+	for (auto &cell_it : module->cells_) {
 		if (!design->selected(module, cell_it.second))
 			continue;
 		if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
-- 
cgit v1.2.3


From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 10:18:00 +0200
Subject: Refactoring: Renamed RTLIL::Design::modules to modules_

---
 passes/memory/memory_dff.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index bb8b052dc..9a1e96796 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -212,7 +212,7 @@ struct MemoryDffPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				handle_module(design, mod_it.second, flag_wr_only);
 	}
-- 
cgit v1.2.3


From 49f72421d5ec499da5da713466e058aae2a67436 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 10:41:42 +0200
Subject: Using new obj iterator API in a few places

---
 passes/memory/memory_dff.cc | 26 +++++++++++---------------
 1 file changed, 11 insertions(+), 15 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 9a1e96796..85249142e 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -38,10 +38,8 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 		if (bit.wire == NULL)
 			continue;
 
-		for (auto &cell_it : module->cells_)
+		for (auto cell : module->cells())
 		{
-			RTLIL::Cell *cell = cell_it.second;
-
 			if (cell->type != "$dff")
 				continue;
 
@@ -120,14 +118,12 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
 
-	for (auto &cell_it : module->cells_) {
-		RTLIL::Cell *cell = cell_it.second;
+	for (auto cell : module->cells())
 		if (cell->type == "$dff") {
 			RTLIL::SigSpec new_q = cell->get("\\Q");
 			new_q.replace(sig, new_sig);
 			cell->set("\\Q", new_q);
 		}
-	}
 }
 
 static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
@@ -170,13 +166,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 
 static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only)
 {
-	for (auto &cell_it : module->cells_) {
-		if (!design->selected(module, cell_it.second))
+	for (auto cell : module->cells()) {
+		if (!design->selected(module, cell))
 			continue;
-		if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
-				handle_wr_cell(module, cell_it.second);
-		if (!flag_wr_only && cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
-				handle_rd_cell(module, cell_it.second);
+		if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+				handle_wr_cell(module, cell);
+		if (!flag_wr_only && cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+				handle_rd_cell(module, cell);
 	}
 }
 
@@ -212,9 +208,9 @@ struct MemoryDffPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod_it : design->modules_)
-			if (design->selected(mod_it.second))
-				handle_module(design, mod_it.second, flag_wr_only);
+		for (auto mod : design->modules())
+			if (design->selected(mod))
+				handle_module(design, mod, flag_wr_only);
 	}
 } MemoryDffPass;
  
-- 
cgit v1.2.3


From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 28 Jul 2014 11:08:55 +0200
Subject: Using log_assert() instead of assert()

---
 passes/memory/memory_dff.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 85249142e..325056170 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -20,7 +20,6 @@
 #include "kernel/register.h"
 #include "kernel/log.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <sstream>
 
 static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
-- 
cgit v1.2.3


From 1cb25c05b37b0172dbc50e140fe20f25d973dd8a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 13:19:47 +0200
Subject: Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

---
 passes/memory/memory_dff.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 325056170..6cbce781f 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -113,7 +113,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 	sig.sort_and_unify();
 
 	std::stringstream sstr;
-	sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++);
+	sstr << "$memory_dff_disconnected$" << (autoidx++);
 
 	RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
 
-- 
cgit v1.2.3


From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 16:38:54 +0200
Subject: Renamed port access function on RTLIL::Cell, added param access
 functions

---
 passes/memory/memory_dff.cc | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 6cbce781f..e92d726cc 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -43,21 +43,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 				continue;
 
 			if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-				if (cell->get("\\CLK") != clk)
+				if (cell->getPort("\\CLK") != clk)
 					continue;
 				if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
 					continue;
 			}
 
-			RTLIL::SigSpec q_norm = cell->get(after ? "\\D" : "\\Q");
+			RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
 			normalize_sig(module, q_norm);
 
-			RTLIL::SigSpec d = q_norm.extract(bit, &cell->get(after ? "\\Q" : "\\D"));
+			RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
 			if (d.size() != 1)
 				continue;
 
 			bit = d;
-			clk = cell->get("\\CLK");
+			clk = cell->getPort("\\CLK");
 			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 			goto replaced_this_bit;
 		}
@@ -76,29 +76,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
 	bool clk_polarity = 0;
 
-	RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
+	RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
 	if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
 		log("no (compatible) $dff for address input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_data = cell->get("\\DATA");
+	RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
 	if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
 		log("no (compatible) $dff for data input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_en = cell->get("\\EN");
+	RTLIL::SigSpec sig_en = cell->getPort("\\EN");
 	if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
 		log("no (compatible) $dff for enable input found.\n");
 		return;
 	}
 
 	if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-		cell->set("\\CLK", clk);
-		cell->set("\\ADDR", sig_addr);
-		cell->set("\\DATA", sig_data);
-		cell->set("\\EN", sig_en);
+		cell->setPort("\\CLK", clk);
+		cell->setPort("\\ADDR", sig_addr);
+		cell->setPort("\\DATA", sig_data);
+		cell->setPort("\\EN", sig_en);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		log("merged $dff to cell.\n");
@@ -119,9 +119,9 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	for (auto cell : module->cells())
 		if (cell->type == "$dff") {
-			RTLIL::SigSpec new_q = cell->get("\\Q");
+			RTLIL::SigSpec new_q = cell->getPort("\\Q");
 			new_q.replace(sig, new_sig);
-			cell->set("\\Q", new_q);
+			cell->setPort("\\Q", new_q);
 		}
 }
 
@@ -132,13 +132,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	bool clk_polarity = 0;
 
 	RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_data = cell->get("\\DATA");
+	RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
 	if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) &&
 			clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
 		disconnect_dff(module, sig_data);
-		cell->set("\\CLK", clk_data);
-		cell->set("\\DATA", sig_data);
+		cell->setPort("\\CLK", clk_data);
+		cell->setPort("\\DATA", sig_data);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
@@ -147,12 +147,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
+	RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
 	if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) &&
 			clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
-		cell->set("\\CLK", clk_addr);
-		cell->set("\\ADDR", sig_addr);
+		cell->setPort("\\CLK", clk_addr);
+		cell->setPort("\\ADDR", sig_addr);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
-- 
cgit v1.2.3


From b4f10e342cf400bd2f392a588f28de069ba0f9d8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 6 Aug 2014 14:31:38 +0200
Subject: Various improvements in memory_dff pass

---
 passes/memory/memory_dff.cc | 43 ++++++++++++++++++++++---------------------
 1 file changed, 22 insertions(+), 21 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index e92d726cc..cdd0b85e2 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -28,7 +28,7 @@ static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
 		sig.replace(conn.first, conn.second);
 }
 
-static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
+static bool find_sig_before_dff(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
 {
 	normalize_sig(module, sig);
 
@@ -37,11 +37,8 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 		if (bit.wire == NULL)
 			continue;
 
-		for (auto cell : module->cells())
+		for (auto cell : dff_cells)
 		{
-			if (cell->type != "$dff")
-				continue;
-
 			if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
 				if (cell->getPort("\\CLK") != clk)
 					continue;
@@ -69,7 +66,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 	return true;
 }
 
-static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
+static void handle_wr_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
 {
 	log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
 
@@ -77,19 +74,19 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	bool clk_polarity = 0;
 
 	RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
-	if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
+	if (!find_sig_before_dff(module, dff_cells, sig_addr, clk, clk_polarity)) {
 		log("no (compatible) $dff for address input found.\n");
 		return;
 	}
 
 	RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
-	if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
+	if (!find_sig_before_dff(module, dff_cells, sig_data, clk, clk_polarity)) {
 		log("no (compatible) $dff for data input found.\n");
 		return;
 	}
 
 	RTLIL::SigSpec sig_en = cell->getPort("\\EN");
-	if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
+	if (!find_sig_before_dff(module, dff_cells, sig_en, clk, clk_polarity)) {
 		log("no (compatible) $dff for enable input found.\n");
 		return;
 	}
@@ -102,6 +99,7 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		log("merged $dff to cell.\n");
+		return;
 	}
 
 	log("no (compatible) $dff found.\n");
@@ -125,7 +123,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 		}
 }
 
-static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
+static void handle_rd_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
 {
 	log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
 
@@ -133,7 +131,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
 	RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
-	if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) &&
+	if (find_sig_before_dff(module, dff_cells, sig_data, clk_data, clk_polarity, true) &&
 			clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
 		disconnect_dff(module, sig_data);
@@ -148,7 +146,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
 	RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
-	if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) &&
+	if (find_sig_before_dff(module, dff_cells, sig_addr, clk_addr, clk_polarity) &&
 			clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
 		cell->setPort("\\CLK", clk_addr);
@@ -163,15 +161,19 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	log("no (compatible) $dff found.\n");
 }
 
-static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only)
+static void handle_module(RTLIL::Module *module, bool flag_wr_only)
 {
-	for (auto cell : module->cells()) {
-		if (!design->selected(module, cell))
-			continue;
+	std::vector<RTLIL::Cell*> dff_cells;
+
+	for (auto cell : module->cells())
+		if (cell->type == "$dff")
+			dff_cells.push_back(cell);
+
+	for (auto cell : module->selected_cells()) {
 		if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
-				handle_wr_cell(module, cell);
+				handle_wr_cell(module, dff_cells, cell);
 		if (!flag_wr_only && cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
-				handle_rd_cell(module, cell);
+				handle_rd_cell(module, dff_cells, cell);
 	}
 }
 
@@ -207,9 +209,8 @@ struct MemoryDffPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto mod : design->modules())
-			if (design->selected(mod))
-				handle_module(design, mod, flag_wr_only);
+		for (auto mod : design->selected_modules())
+			handle_module(mod, flag_wr_only);
 	}
 } MemoryDffPass;
  
-- 
cgit v1.2.3


From ae02d9cb9a990bfbe76d056fd341d88a9a5f129c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 16 Sep 2014 12:40:58 +0200
Subject: Fixed $memwr/$memrd order in memory_dff

---
 passes/memory/memory_dff.cc | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

(limited to 'passes/memory/memory_dff.cc')

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index cdd0b85e2..302ab3abf 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -169,12 +169,14 @@ static void handle_module(RTLIL::Module *module, bool flag_wr_only)
 		if (cell->type == "$dff")
 			dff_cells.push_back(cell);
 
-	for (auto cell : module->selected_cells()) {
+	for (auto cell : module->selected_cells())
 		if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
-				handle_wr_cell(module, dff_cells, cell);
-		if (!flag_wr_only && cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+			handle_wr_cell(module, dff_cells, cell);
+
+	if (!flag_wr_only)
+		for (auto cell : module->selected_cells())
+			if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
 				handle_rd_cell(module, dff_cells, cell);
-	}
 }
 
 struct MemoryDffPass : public Pass {
-- 
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