From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- passes/memory/memory_collect.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'passes/memory/memory_collect.cc') diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index b4242f250..a8caf883f 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -76,12 +76,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) wr_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections_["\\CLK"]; + RTLIL::SigSpec clk = cell->get("\\CLK"); RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); - RTLIL::SigSpec addr = cell->connections_["\\ADDR"]; - RTLIL::SigSpec data = cell->connections_["\\DATA"]; - RTLIL::SigSpec en = cell->connections_["\\EN"]; + RTLIL::SigSpec addr = cell->get("\\ADDR"); + RTLIL::SigSpec data = cell->get("\\DATA"); + RTLIL::SigSpec en = cell->get("\\EN"); clk.extend(1, false); clk_enable.extend(1, false); @@ -103,12 +103,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) rd_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections_["\\CLK"]; + RTLIL::SigSpec clk = cell->get("\\CLK"); RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]); - RTLIL::SigSpec addr = cell->connections_["\\ADDR"]; - RTLIL::SigSpec data = cell->connections_["\\DATA"]; + RTLIL::SigSpec addr = cell->get("\\ADDR"); + RTLIL::SigSpec data = cell->get("\\DATA"); clk.extend(1, false); clk_enable.extend(1, false); @@ -147,10 +147,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); - mem->connections_["\\WR_CLK"] = sig_wr_clk; - mem->connections_["\\WR_ADDR"] = sig_wr_addr; - mem->connections_["\\WR_DATA"] = sig_wr_data; - mem->connections_["\\WR_EN"] = sig_wr_en; + mem->set("\\WR_CLK", sig_wr_clk); + mem->set("\\WR_ADDR", sig_wr_addr); + mem->set("\\WR_DATA", sig_wr_data); + mem->set("\\WR_EN", sig_wr_en); assert(sig_rd_clk.size() == rd_ports); assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); @@ -163,9 +163,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); - mem->connections_["\\RD_CLK"] = sig_rd_clk; - mem->connections_["\\RD_ADDR"] = sig_rd_addr; - mem->connections_["\\RD_DATA"] = sig_rd_data; + mem->set("\\RD_CLK", sig_rd_clk); + mem->set("\\RD_ADDR", sig_rd_addr); + mem->set("\\RD_DATA", sig_rd_data); for (auto c : del_cells) module->remove(c); -- cgit v1.2.3