From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- passes/hierarchy/hierarchy.cc | 4 ++-- passes/hierarchy/submod.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'passes/hierarchy') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 8aec25eba..c869ec729 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -98,7 +98,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell generate_port_decl_t d = decl; d.portname = portname; d.index = *indices.begin(); - assert(!indices.empty()); + log_assert(!indices.empty()); indices.erase(d.index); ports[d.index-1] = d; portwidths[d.portname] = std::max(portwidths[d.portname], 1); @@ -110,7 +110,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell portnames.erase(portname); } - assert(indices.empty()); + log_assert(indices.empty()); RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d32b5e1d3..84c6b9161 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -171,7 +171,7 @@ struct SubmodWorker for (auto &conn : new_cell->connections_) for (auto &bit : conn.second) if (bit.wire != NULL) { - assert(wire_flags.count(bit.wire) > 0); + log_assert(wire_flags.count(bit.wire) > 0); bit.wire = wire_flags[bit.wire].new_wire; } log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); -- cgit v1.2.3