From 7f734ecc098a2a113ced835cefc9d4e1982f08d0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 23:50:36 +0200 Subject: Added module->uniquify() --- passes/fsm/fsm_map.cc | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'passes/fsm') diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 60580eb46..ab6d5671d 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -163,11 +163,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // create state register - std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string(); - while (module->count_id(state_wire_name) > 0) - state_wire_name += "_"; - - RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits); + RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits); RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); -- cgit v1.2.3