From f8b97e21f3f76dd031f82586f8af104368f03e73 Mon Sep 17 00:00:00 2001 From: rafaeltp Date: Sun, 21 Oct 2018 11:32:44 -0700 Subject: using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal --- passes/equiv/equiv_make.cc | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) (limited to 'passes/equiv/equiv_make.cc') diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index cfb4d4438..dbd8682e6 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -298,20 +298,21 @@ struct EquivMakeWorker SigSpec new_sig = rd_signal_map(old_sig); if(old_sig != new_sig) { - for (auto &old_bit : old_sig.bits()) { - SigBit new_bit = new_sig.bits()[old_bit.offset]; + SigSpec tmp_sig = old_sig; + for (int i = 0; i < GetSize(old_sig); i++) { + SigBit old_bit = old_sig[i], new_bit = new_sig[i]; visited_cells.clear(); - if (old_bit != new_bit) { - if (check_signal_in_fanout(visited_cells, old_bit, new_bit)) - continue; - - log("Changing input %s of cell %s (%s): %s -> %s\n", - log_id(conn.first), log_id(c), log_id(c->type), - log_signal(old_bit), log_signal(new_bit)); - c->setPort(conn.first, new_bit); - } + if (check_signal_in_fanout(visited_cells, old_bit, new_bit)) + continue; + + log("Changing input %s of cell %s (%s): %s -> %s\n", + log_id(conn.first), log_id(c), log_id(c->type), + log_signal(old_bit), log_signal(new_bit)); + + tmp_sig[i] = new_bit; } + c->setPort(conn.first, tmp_sig); } } -- cgit v1.2.3