From 4cd6d5556ade3a6da64d3639e6b6e547222820e8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Jun 2018 11:49:58 +0200 Subject: Add "setundef -anyconst" Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 61 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 20 deletions(-) (limited to 'passes/cmds') diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index c11ddbdc1..be26c3fd4 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -23,6 +23,13 @@ #include "kernel/rtlil.h" #include "kernel/log.h" +#define MODE_ZERO 0 +#define MODE_ONE 1 +#define MODE_UNDEF 2 +#define MODE_RANDOM 3 +#define MODE_ANYSEQ 4 +#define MODE_ANYCONST 5 + USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -34,30 +41,32 @@ struct SetundefWorker RTLIL::State next_bit() { - if (next_bit_mode == 0) + if (next_bit_mode == MODE_ZERO) return RTLIL::State::S0; - if (next_bit_mode == 1) + if (next_bit_mode == MODE_ONE) return RTLIL::State::S1; - if (next_bit_mode == 2) - log_abort(); - - if (next_bit_mode == 4) + if (next_bit_mode == MODE_UNDEF) return RTLIL::State::Sx; - // xorshift32 - next_bit_state ^= next_bit_state << 13; - next_bit_state ^= next_bit_state >> 17; - next_bit_state ^= next_bit_state << 5; - log_assert(next_bit_state != 0); + if (next_bit_mode == MODE_RANDOM) + { + // xorshift32 + next_bit_state ^= next_bit_state << 13; + next_bit_state ^= next_bit_state >> 17; + next_bit_state ^= next_bit_state << 5; + log_assert(next_bit_state != 0); + + return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1; + } - return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1; + log_abort(); } void operator()(RTLIL::SigSpec &sig) { - if (next_bit_mode == 2) { + if (next_bit_mode == MODE_ANYSEQ || next_bit_mode == MODE_ANYCONST) { siglist.push_back(&sig); return; } @@ -93,6 +102,9 @@ struct SetundefPass : public Pass { log(" -anyseq\n"); log(" replace with $anyseq drivers (for formal)\n"); log("\n"); + log(" -anyconst\n"); + log(" replace with $anyconst drivers (for formal)\n"); + log("\n"); log(" -random \n"); log(" replace with random bits using the specified integer als seed\n"); log(" value for the random number generator.\n"); @@ -119,25 +131,31 @@ struct SetundefPass : public Pass { } if (args[argidx] == "-zero") { got_value = true; - worker.next_bit_mode = 0; + worker.next_bit_mode = MODE_ZERO; worker.next_bit_state = 0; continue; } if (args[argidx] == "-one") { got_value = true; - worker.next_bit_mode = 1; + worker.next_bit_mode = MODE_ONE; worker.next_bit_state = 0; continue; } if (args[argidx] == "-anyseq") { got_value = true; - worker.next_bit_mode = 2; + worker.next_bit_mode = MODE_ANYSEQ; + worker.next_bit_state = 0; + continue; + } + if (args[argidx] == "-anyconst") { + got_value = true; + worker.next_bit_mode = MODE_ANYCONST; worker.next_bit_state = 0; continue; } if (args[argidx] == "-undef") { got_value = true; - worker.next_bit_mode = 4; + worker.next_bit_mode = MODE_UNDEF; worker.next_bit_state = 0; continue; } @@ -147,7 +165,7 @@ struct SetundefPass : public Pass { } if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; - worker.next_bit_mode = 3; + worker.next_bit_mode = MODE_RANDOM; worker.next_bit_state = atoi(args[++argidx].c_str()) + 1; for (int i = 0; i < 10; i++) worker.next_bit(); @@ -274,7 +292,7 @@ struct SetundefPass : public Pass { module->rewrite_sigspecs(worker); - if (worker.next_bit_mode == 2) + if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST) { vector siglist; siglist.swap(worker.siglist); @@ -291,7 +309,10 @@ struct SetundefPass : public Pass { width++; if (width > 0) { - sig.replace(cursor, module->Anyseq(NEW_ID, width)); + if (worker.next_bit_mode == MODE_ANYSEQ) + sig.replace(cursor, module->Anyseq(NEW_ID, width)); + else + sig.replace(cursor, module->Anyconst(NEW_ID, width)); cursor += width; } else { cursor++; -- cgit v1.2.3 From f273291dfe5de460192ef2a63a121b3c2e8b9a62 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Jun 2018 11:57:28 +0200 Subject: Add setundef -anyseq / -anyconst support to -undriven mode Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'passes/cmds') diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index be26c3fd4..3a3ebedf1 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -176,7 +176,10 @@ struct SetundefPass : public Pass { extra_args(args, argidx, design); if (!got_value) - log_cmd_error("One of the options -zero, -one, -anyseq, or -random must be specified.\n"); + log_cmd_error("One of the options -zero, -one, -anyseq, -anyconst, or -random must be specified.\n"); + + if (init_mode && (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)) + log_cmd_error("The options -init and -anyseq / -anyconst are exclusive.\n"); for (auto module : design->selected_modules()) { @@ -204,8 +207,13 @@ struct SetundefPass : public Pass { RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; - for (int i = 0; i < c.width; i++) - bits.append(worker.next_bit()); + if (worker.next_bit_mode == MODE_ANYSEQ) + bits = module->Anyseq(NEW_ID, c.width); + else if (worker.next_bit_mode == MODE_ANYCONST) + bits = module->Anyconst(NEW_ID, c.width); + else + for (int i = 0; i < c.width; i++) + bits.append(worker.next_bit()); module->connect(RTLIL::SigSig(c, bits)); } } -- cgit v1.2.3 From d89560a0ba6402a8d13177909cc2c1f3b8b7c3e2 Mon Sep 17 00:00:00 2001 From: Edmond Cote Date: Mon, 18 Jun 2018 17:29:01 -0700 Subject: Include module name for area summary stats The PR prints the name of the module when displaying the final area count. Pros: - Easier for the user to `grep` for area information about a specific module Cons: - Arguably more verbose, less "pretty" than author desires Verification: ~~~~ 30c30 < Chip area for this module: 20616.349000 --- > Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000 70c70 < Chip area for this module: 88.697700 --- > Chip area for module '\picorv32_axi_adapter': 88.697700 102c102 < Chip area for this module: 20705.046700 --- > Chip area for top module '\picorv32_axi': 20705.046700 ~~~~ --- passes/cmds/stat.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes/cmds') diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index e52a192db..f1d958a1a 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -142,7 +142,7 @@ struct statdata_t } } - void log_data() + void log_data(RTLIL::IdString mod_name, bool top_mod) { log(" Number of wires: %6d\n", num_wires); log(" Number of wire bits: %6d\n", num_wire_bits); @@ -163,7 +163,7 @@ struct statdata_t if (area != 0) { log("\n"); - log(" Chip area for this module: %f\n", area); + log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area); } } }; @@ -275,7 +275,7 @@ struct StatPass : public Pass { log("\n"); log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)"); log("\n"); - data.log_data(); + data.log_data(mod->name, false); } if (top_mod != NULL && GetSize(mod_stat) > 1) @@ -288,7 +288,7 @@ struct StatPass : public Pass { statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0); log("\n"); - data.log_data(); + data.log_data(top_mod->name, true); } log("\n"); -- cgit v1.2.3