From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jul 2014 01:51:45 +0200
Subject: Refactoring: Renamed RTLIL::Module::cells to cells_

---
 passes/cmds/connwrappers.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'passes/cmds/connwrappers.cc')

diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 9faeffafa..cc8147c53 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -67,7 +67,7 @@ struct ConnwrappersWorker
 		std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map;
 		SigMap sigmap(module);
 
-		for (auto &it : module->cells)
+		for (auto &it : module->cells_)
 		{
 			RTLIL::Cell *cell = it.second;
 
@@ -102,7 +102,7 @@ struct ConnwrappersWorker
 			}
 		}
 
-		for (auto &it : module->cells)
+		for (auto &it : module->cells_)
 		{
 			RTLIL::Cell *cell = it.second;
 
-- 
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