From a8d3a68971ccc4e47c54a906aae374a9a54b1415 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 23 Jul 2014 08:40:31 +0200
Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor --
 step 2/3

---
 passes/abc/abc.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes/abc')

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index e7371ec52..fa2c49604 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 			clk_str = clk_str.substr(1);
 		}
 		if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
-			clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1, 0));
+			clk_sig = assign_map(RTLIL::SigSpec::grml(module->wires.at(RTLIL::escape_id(clk_str)), 0));
 	}
 
 	if (dff_mode && clk_sig.size() == 0)
-- 
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