From e0e6d130cd083a8285ea2991629e0049023da234 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 19 Feb 2015 13:36:54 +0100 Subject: YosysJS stuff --- misc/yosysjs/demo03.html | 103 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 misc/yosysjs/demo03.html (limited to 'misc/yosysjs/demo03.html') diff --git a/misc/yosysjs/demo03.html b/misc/yosysjs/demo03.html new file mode 100644 index 000000000..720b82e90 --- /dev/null +++ b/misc/yosysjs/demo03.html @@ -0,0 +1,103 @@ + +YosysJS Example Application #02 + + + + + + + +

YosysJS Example Application #03

+ Your mission: Create a behavioral Verilog model for the following circuit: +

+ +

+ 

module top(input clk, reset, input [7:0] A, output reg [7:0] Y);
+  always @(posedge clock) begin
+    Y <= A | {4{reset}};
+  end
+endmodule

+ +

+

 

+ + -- cgit v1.2.3 From 78b991d760d52311c09287a2e20270c83c069b6c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 19 Feb 2015 13:55:36 +0100 Subject: YosysJS firefox fixes --- misc/yosysjs/demo03.html | 3 --- 1 file changed, 3 deletions(-) (limited to 'misc/yosysjs/demo03.html') diff --git a/misc/yosysjs/demo03.html b/misc/yosysjs/demo03.html index 720b82e90..36cc6cf4a 100644 --- a/misc/yosysjs/demo03.html +++ b/misc/yosysjs/demo03.html @@ -58,7 +58,6 @@ endmodule

} else { wdata = ys.read_file('wave.json'); if (wdata) { - console.log(wdata) wdata = JSON.parse(wdata); function wsignal(signame, newname) { for (i = 0; i < wdata["signal"].length; i++) @@ -81,7 +80,6 @@ endmodule

"config" : wdata["config"] }; wdata2 = JSON.stringify(wdata2) - console.log(wdata2) w.innerHTML = 'The model did not pass verification:

' + ' -- cgit v1.2.3 From 1fe15a5973bcd7b5d07ea82fd85545a6e73a20f0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 21 Feb 2015 14:25:34 +0100 Subject: YosysJS: Wait for Viz to load --- misc/yosysjs/demo03.html | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'misc/yosysjs/demo03.html') diff --git a/misc/yosysjs/demo03.html b/misc/yosysjs/demo03.html index 36cc6cf4a..c9386aee8 100644 --- a/misc/yosysjs/demo03.html +++ b/misc/yosysjs/demo03.html @@ -24,16 +24,18 @@ endmodule

YosysJS Example Application #03

Your mission: Create a behavioral Verilog model for the following circuit:

- -

- 

module top(input clk, reset, input [7:0] A, output reg [7:0] Y);
-  always @(posedge clock) begin
-    Y <= A | {4{reset}};
-  end
-endmodule

- -

-

 

+