From 1eec255e60f2854b4dd1fa212f02d57eb31c9f19 Mon Sep 17 00:00:00 2001 From: KrystalDelusion Date: Thu, 8 Dec 2022 05:54:08 +1300 Subject: Removing manual files --- manual/manual.tex | 230 ------------------------------------------------------ 1 file changed, 230 deletions(-) delete mode 100644 manual/manual.tex (limited to 'manual/manual.tex') diff --git a/manual/manual.tex b/manual/manual.tex deleted file mode 100644 index 1914df989..000000000 --- a/manual/manual.tex +++ /dev/null @@ -1,230 +0,0 @@ -\documentclass[oneside,a4paper]{book} - -\usepackage[T1]{fontenc} % required for luximono! -\usepackage{lmodern} -\usepackage[scaled=0.8]{luximono} % typewriter font with bold face - -% To install the luximono font files: -% getnonfreefonts-sys --all or -% getnonfreefonts-sys luximono -% -% when there are trouble you might need to: -% - Create /etc/texmf/updmap.d/99local-luximono.cfg -% containing the single line: Map ul9.map -% - Run update-updmap followed by mktexlsr and updmap-sys -% -% This commands must be executed as root with a root environment -% (i.e. run "sudo su" and then execute the commands in the root -% shell, don't just prefix the commands with "sudo"). - -% formats the text according the set language -\usepackage[english]{babel} -\usepackage[table,usenames]{xcolor} -% generates indices with the "\index" command -\usepackage{makeidx} -% enables import of graphics. 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In these cases the -availability of a Free and Open Source (FOSS) synthesis tool that can be used -as basis for custom tools would be helpful. - -In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was -developed. This document covers the design and implementation of this tool. -At the moment the main focus of Yosys lies on the high-level aspects of -digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used -by Yosys to perform advanced gate-level optimizations. - -An evaluation of Yosys based on real-world designs is included. It is shown -that Yosys can be used as-is to synthesize such designs. The results produced -by Yosys in this tests where successfully verified using formal verification -and are comparable in quality to the results produced by a commercial -synthesis tool. - -\bigskip - -This document was originally published as bachelor thesis at the Vienna -University of Technology \cite{BACC}. - -\chapter*{Abbreviations} -\begin{tabular}{ll} -AIG & And-Inverter-Graph \\ -ASIC & Application-Specific Integrated Circuit \\ -AST & Abstract Syntax Tree \\ -BDD & Binary Decision Diagram \\ -BLIF & Berkeley Logic Interchange Format \\ -EDA & Electronic Design Automation \\ -EDIF & Electronic Design Interchange Format \\ -ER Diagram & Entity-Relationship Diagram \\ -FOSS & Free and Open-Source Software \\ -FPGA & Field-Programmable Gate Array \\ -FSM & Finite-state machine \\ -HDL & Hardware Description Language \\ -LPM & Library of Parameterized Modules \\ -RTLIL & RTL Intermediate Language \\ -RTL & Register Transfer Level \\ -SAT & Satisfiability Problem \\ -% SSA & Static Single Assignment Form \\ -VHDL & VHSIC Hardware Description Language \\ -VHSIC & Very-High-Speed Integrated Circuit \\ -YOSYS & Yosys Open SYnthesis Suite \\ -\end{tabular} - -\tableofcontents - -\include{CHAPTER_Intro} -\include{CHAPTER_Basics} -\include{CHAPTER_Approach} -\include{CHAPTER_Overview} -\include{CHAPTER_CellLib} -\include{CHAPTER_Prog} - -\include{CHAPTER_Verilog} -\include{CHAPTER_Optimize} -\include{CHAPTER_Techmap} -% \include{CHAPTER_Eval} - -\appendix - -\include{CHAPTER_Auxlibs} -\include{CHAPTER_Auxprogs} - -\chapter{Command Reference Manual} -\label{commandref} -\input{command-reference-manual} - -\include{CHAPTER_TextRtlil} -\include{CHAPTER_Appnotes} -% \include{CHAPTER_StateOfTheArt} - -\bibliography{literature} -\bibliographystyle{alphadin} - -\bibliographyweblink{weblinks} -\bibliographystyleweblink{abbrv} - -\end{document} -- cgit v1.2.3