From a62c21c9c64ad5b3e0dae5d4ee4857425f73068e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 16:09:27 +0200 Subject: Removed RTLIL::SigSpec::expand() method --- manual/CHAPTER_Prog/stubnets.cc | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) (limited to 'manual/CHAPTER_Prog') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 1c71f78b8..efb3ca958 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -21,7 +21,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re SigMap sigmap(module); // count how many times a single-bit signal is used - std::map bit_usage_count; + std::map bit_usage_count; // count ouput lines for this module (needed only for summary output at the end) int line_count = 0; @@ -36,13 +36,10 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // (use sigmap to get a uniqe signal name) RTLIL::SigSpec sig = sigmap(conn.second); - // split the signal up into single-bit chunks - sig.expand(); - - // add each chunk to bit_usage_count, unless it is a constant - for (auto &c : sig.chunks) - if (c.wire != NULL) - bit_usage_count[c]++; + // add each bit to bit_usage_count, unless it is a constant + for (auto &bit : sig) + if (bit.wire != NULL) + bit_usage_count[bit]++; } // for each wire in the module @@ -62,13 +59,11 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // get a signal description for this wire and split it into seperate bits RTLIL::SigSpec sig = sigmap(wire); - sig.expand(); // for each bit (unless it is a constant): // check if it is used at least two times and add to stub_bits otherwise - for (size_t i = 0; i < sig.chunks.size(); i++) - if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] + - usage_offset) < 2) + for (size_t i = 0; i < SIZE(sig); i++) + if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2) stub_bits.insert(i); // continue if no stub bits found -- cgit v1.2.3 From 3ec785b881a7bbceb5ac4db1e761b75c07f8642a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 19:36:43 +0200 Subject: Fixed manual/CHAPTER_Prog/stubnets.cc --- manual/CHAPTER_Prog/stubnets.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'manual/CHAPTER_Prog') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index efb3ca958..3f8d553ad 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -62,7 +62,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // for each bit (unless it is a constant): // check if it is used at least two times and add to stub_bits otherwise - for (size_t i = 0; i < SIZE(sig); i++) + for (int i = 0; i < SIZE(sig); i++) if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2) stub_bits.insert(i); @@ -72,7 +72,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // report stub bits and/or stub wires, don't report single bits // if called with report_bits set to false. - if (int(stub_bits.size()) == sig.width) { + if (SIZE(stub_bits) == SIZE(sig)) { log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name)); } else { if (!report_bits) -- cgit v1.2.3 From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- manual/CHAPTER_Prog/stubnets.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual/CHAPTER_Prog') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 3f8d553ad..f6c1528ee 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -30,7 +30,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // For all ports on all cells for (auto &cell_iter : module->cells) - for (auto &conn : cell_iter.second->connections) + for (auto &conn : cell_iter.second->connections_) { // Get the signals on the port // (use sigmap to get a uniqe signal name) -- cgit v1.2.3 From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- manual/CHAPTER_Prog/stubnets.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual/CHAPTER_Prog') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index f6c1528ee..f67ffe1e8 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -30,7 +30,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // For all ports on all cells for (auto &cell_iter : module->cells) - for (auto &conn : cell_iter.second->connections_) + for (auto &conn : cell_iter.second->connections()) { // Get the signals on the port // (use sigmap to get a uniqe signal name) -- cgit v1.2.3 From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- manual/CHAPTER_Prog/stubnets.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual/CHAPTER_Prog') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index f67ffe1e8..9eacfbcb5 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -43,7 +43,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re } // for each wire in the module - for (auto &wire_iter : module->wires) + for (auto &wire_iter : module->wires_) { RTLIL::Wire *wire = wire_iter.second; -- cgit v1.2.3 From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- manual/CHAPTER_Prog/stubnets.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual/CHAPTER_Prog') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 9eacfbcb5..a57907435 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -29,7 +29,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name)); // For all ports on all cells - for (auto &cell_iter : module->cells) + for (auto &cell_iter : module->cells_) for (auto &conn : cell_iter.second->connections()) { // Get the signals on the port -- cgit v1.2.3 From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- manual/CHAPTER_Prog/stubnets.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual/CHAPTER_Prog') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index a57907435..4d1452c97 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -120,7 +120,7 @@ struct StubnetsPass : public Pass { // call find_stub_nets() for each module that is either // selected as a whole or contains selected objects. - for (auto &it : design->modules) + for (auto &it : design->modules_) if (design->selected_module(it.first)) find_stub_nets(design, it.second, report_bits); } -- cgit v1.2.3 From 79cbf9067c07ed810b3466174278d77b9a05b46d Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Sat, 6 Sep 2014 08:47:06 +0200 Subject: Corrected spelling mistakes found by lintian --- manual/CHAPTER_Prog/stubnets.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'manual/CHAPTER_Prog') diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 4d1452c97..ef4b1245d 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -57,7 +57,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // we will record which bits of the (possibly multi-bit) wire are stub signals std::set stub_bits; - // get a signal description for this wire and split it into seperate bits + // get a signal description for this wire and split it into separate bits RTLIL::SigSpec sig = sigmap(wire); // for each bit (unless it is a constant): -- cgit v1.2.3