From 84bf862f7c58c2b69babf043ff5032f924a3ee4d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 14 Aug 2015 10:56:05 +0200
Subject: Spell check (by Larry Doolittle)

---
 manual/CHAPTER_CellLib.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'manual/CHAPTER_CellLib.tex')

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index c9bf978a9..9f9ec2e2b 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -104,7 +104,7 @@ Multiplexers are generated by the Verilog HDL frontend for {\tt
 from RTLIL::Process objects to logic.
 
 The simplest multiplexer cell type is {\tt \$mux}. Cells of this type have a \B{WIDTH} parameter
-and data inputs \B{A} and \B{B} and a data ouput \B{Y}, all of the specified width. This cell also
+and data inputs \B{A} and \B{B} and a data output \B{Y}, all of the specified width. This cell also
 has a single bit control input \B{S}. If \B{S} is 0 the value from the \B{A} input is sent to
 the output, if it is 1 the value from the \B{B} input is sent to the output. So the {\tt \$mux}
 cell implements the function \lstinline[language=Verilog]; Y = S ? B : A;.
@@ -399,7 +399,7 @@ represent d-type flip-flops.
 The cell types {\tt \$\_DFF\_NN0\_}, {\tt \$\_DFF\_NN1\_}, {\tt \$\_DFF\_NP0\_}, {\tt \$\_DFF\_NP1\_},
 {\tt \$\_DFF\_PN0\_}, {\tt \$\_DFF\_PN1\_}, {\tt \$\_DFF\_PP0\_} and {\tt \$\_DFF\_PP1\_} implement
 d-type flip-flops with asynchronous resets. The values in the table for these cell types relate to the
-following verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
+following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
 if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, and \lstinline[language=Verilog];negedge;
 otherwise.
 
-- 
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