From dd6d34f461910a120ac95c485fe34cca6485b95e Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 17 Mar 2021 12:06:09 +0000 Subject: blackbox: Include whiteboxed modules Signed-off-by: gatecat --- kernel/rtlil.cc | 4 ++-- kernel/rtlil.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 32069ce03..87cbaa0d5 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -808,12 +808,12 @@ std::vector RTLIL::Design::selected_whole_modules() const return result; } -std::vector RTLIL::Design::selected_whole_modules_warn() const +std::vector RTLIL::Design::selected_whole_modules_warn(bool include_wb) const { std::vector result; result.reserve(modules_.size()); for (auto &it : modules_) - if (it.second->get_blackbox_attribute()) + if (it.second->get_blackbox_attribute(include_wb)) continue; else if (selected_whole_module(it.first)) result.push_back(it.second); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a747b9d3c..bbdf355fa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1112,7 +1112,7 @@ struct RTLIL::Design std::vector selected_modules() const; std::vector selected_whole_modules() const; - std::vector selected_whole_modules_warn() const; + std::vector selected_whole_modules_warn(bool include_wb = false) const; #ifdef WITH_PYTHON static std::map *get_all_designs(void); #endif -- cgit v1.2.3