From 93bc5affd3fc635dafec3a37bf4c5b94c252036f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Mon, 8 Jul 2019 11:34:58 +0000
Subject: Allow attributes on individual switch cases in RTLIL.

The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
---
 kernel/rtlil.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'kernel')

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index f4fcf5dcf..82cbfaf28 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1327,7 +1327,7 @@ public:
 #endif
 };
 
-struct RTLIL::CaseRule
+struct RTLIL::CaseRule : public RTLIL::AttrObject
 {
 	std::vector<RTLIL::SigSpec> compare;
 	std::vector<RTLIL::SigSig> actions;
-- 
cgit v1.2.3


From 41d7d9d24b8ba7fd84dd72b27eb9aede10b8ef15 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 19:21:21 -0700
Subject: Clarify script -scriptwire doc

---
 kernel/yosys.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'kernel')

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index f95c0127b..a42a7c0b8 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -1273,6 +1273,10 @@ struct ScriptCmdPass : public Pass {
 		log("If only one label is specified (without ':') then only the block\n");
 		log("marked with that label (until the next label) is executed.\n");
 		log("\n");
+		log("In \"-scriptwire\" mode, the commands on the selected wire(s) will be executed\n");
+		log("in the scope of (and thus, relative to) the wires' owning module(s). This\n");
+		log("'-module' mode can be exited by using the 'cd' command.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-- 
cgit v1.2.3