From a63e2508fcca395e795029d5c57c59acc63a9959 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 7 Jan 2020 12:52:03 -0800 Subject: Add RTLIL::constpad, init by yosys_setup(); use for abc9 --- kernel/rtlil.cc | 1 + kernel/rtlil.h | 2 ++ kernel/yosys.cc | 9 +++++++++ 3 files changed, 12 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ab4f4f377..f286d139f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -46,6 +46,7 @@ IdString RTLIL::ID::Y; IdString RTLIL::ID::keep; IdString RTLIL::ID::whitebox; IdString RTLIL::ID::blackbox; +dict RTLIL::constpad; RTLIL::Const::Const() { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e5b24cc02..6251d265d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -377,6 +377,8 @@ namespace RTLIL extern IdString blackbox; }; + extern dict constpad; + static inline std::string escape_id(std::string str) { if (str.size() > 0 && str[0] != '\\' && str[0] != '$') return "\\" + str; diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 5018a4888..6c8427c19 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -524,6 +524,15 @@ void yosys_setup() PyRun_SimpleString("import sys"); #endif + RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -v; &mfs"; + RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -a -v; &mfs"; + RTLIL::constpad["abc9.script.default.fast"] = "&if {W} {D}"; + RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \ + "&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} -v; &save; &load; "\ + "&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} -v; &save; &load; "\ + "&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} -v; &save; &load; "\ + "&mfs"; + Pass::init_register(); yosys_design = new RTLIL::Design; yosys_celltypes.setup(); -- cgit v1.2.3 From fbd9636e08b9a4ac5e58161ca6a6b5308cd795cb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 8 Jan 2020 12:15:01 -0800 Subject: Add abc9.if.script.flow{,2} to constpad --- kernel/yosys.cc | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 6c8427c19..cd6955c3f 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -524,13 +524,39 @@ void yosys_setup() PyRun_SimpleString("import sys"); #endif - RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -v; &mfs"; - RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -a -v; &mfs"; - RTLIL::constpad["abc9.script.default.fast"] = "&if {W} {D}"; + RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs"; + RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs"; + RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}"; + // Based on ABC's &flow + RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \ + /* Round 1 */ \ + "&unmap; &if {C} {W} {D} {R}; &mfs;" \ + "&st; &dsdb;" \ + "&unmap; &if {C} {W} {D} {R}; &mfs;" \ + "&st; &syn2 -m -R 10; &dsdb;" \ + "&blut -a -K 6;" \ + "&unmap; &if {C} {W} {D} {R}; &mfs;" \ + /* Round 2 */ \ + "&st; &sopb;" \ + "&unmap; &if {C} {W} {D} {R}; &mfs;" \ + "&st; &dsdb;" \ + "&unmap; &if {C} {W} {D} {R}; &mfs;" \ + "&st; &syn2 -m -R 10; &dsdb;" \ + "&blut -a -K 6;" \ + "&unmap; &if {C} {W} {D} {R} -v; &mfs"; + // Based on ABC's &flow2 + RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \ + /* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\ + /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\ + "&load; &st; &sopb -R 10 -C 4; " \ + /* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\ + /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\ + "&load"; + // Based on ABC's &flow3 RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \ - "&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} -v; &save; &load; "\ - "&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} -v; &save; &load; "\ - "&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} -v; &save; &load; "\ + "&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\ + "&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\ + "&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\ "&mfs"; Pass::init_register(); -- cgit v1.2.3 From 67c9c41f7e566f5604a3e38e7ad402d6b5c80fd8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 9 Jan 2020 17:10:54 -0800 Subject: Move abc9.* constpad entries to Abc9Pass::on_register() --- kernel/yosys.cc | 35 ----------------------------------- 1 file changed, 35 deletions(-) (limited to 'kernel') diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 6956cbdc3..8190d8902 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -524,41 +524,6 @@ void yosys_setup() PyRun_SimpleString("import sys"); #endif - RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs"; - RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs"; - RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}"; - // Based on ABC's &flow - RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \ - /* Round 1 */ \ - "&unmap; &if {C} {W} {D} {R}; &mfs;" \ - "&st; &dsdb;" \ - "&unmap; &if {C} {W} {D} {R}; &mfs;" \ - "&st; &syn2 -m -R 10; &dsdb;" \ - "&blut -a -K 6;" \ - "&unmap; &if {C} {W} {D} {R}; &mfs;" \ - /* Round 2 */ \ - "&st; &sopb;" \ - "&unmap; &if {C} {W} {D} {R}; &mfs;" \ - "&st; &dsdb;" \ - "&unmap; &if {C} {W} {D} {R}; &mfs;" \ - "&st; &syn2 -m -R 10; &dsdb;" \ - "&blut -a -K 6;" \ - "&unmap; &if {C} {W} {D} {R} -v; &mfs"; - // Based on ABC's &flow2 - RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \ - /* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\ - /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\ - "&load; &st; &sopb -R 10 -C 4; " \ - /* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\ - /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\ - "&load"; - // Based on ABC's &flow3 - RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \ - "&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\ - "&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\ - "&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\ - "&mfs"; - Pass::init_register(); yosys_design = new RTLIL::Design; yosys_celltypes.setup(); -- cgit v1.2.3