From 3cc95fb4be27a3e130563db102ed268876027288 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Apr 2019 21:58:57 +0200 Subject: Add specify parser Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7e1159cac..7d5334eb1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1194,6 +1194,16 @@ namespace { return; } + if (cell->type == "$specify2") { + // FIXME + return; + } + + if (cell->type == "$specify3") { + // FIXME + return; + } + if (cell->type == "$_BUF_") { check_gate("AY"); return; } if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } -- cgit v1.2.3 From e1d73e03d38e9408cc7bce685645bb170ca5a6b8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:26:20 +0200 Subject: Add InternalCellChecker support for $specify2 and $specify3 Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d5334eb1..9e06b8323 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1194,13 +1194,27 @@ namespace { return; } - if (cell->type == "$specify2") { - // FIXME - return; - } - - if (cell->type == "$specify3") { - // FIXME + if (cell->type.in("$specify2", "$specify3")) { + param_bool("\\FULL"); + param_bool("\\SRC_DST_PEN"); + param_bool("\\SRC_DST_POL"); + param("\\T_RISE_MIN"); + param("\\T_RISE_AVG"); + param("\\T_RISE_MAX"); + param("\\T_FALL_MIN"); + param("\\T_FALL_AVG"); + param("\\T_FALL_MAX"); + port("\\EN", 1); + port("\\SRC", param("\\SRC_WIDTH")); + port("\\DST", param("\\DST_WIDTH")); + if (cell->type == "$specify3") { + param_bool("\\EDGE_EN"); + param_bool("\\EDGE_POL"); + param_bool("\\DAT_DST_PEN"); + param_bool("\\DAT_DST_POL"); + port("\\DAT", param("\\DST_WIDTH")); + } + check_expected(); return; } -- cgit v1.2.3 From aec2475a9d7a2a903d5015840a3320ce2cedf5cd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:29:59 +0200 Subject: Add CellTypes support for $specify2 and $specify3 Signed-off-by: Clifford Wolf --- kernel/celltypes.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 0da78c313..f8c73ed83 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -85,6 +85,7 @@ struct CellTypes setup_internals_eval(); IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y"; + IdString SRC = "\\SRC", DST = "\\DST", DAT = "\\DAT"; setup_type("$tribuf", {A, EN}, {Y}, true); @@ -99,6 +100,8 @@ struct CellTypes setup_type("$allconst", pool(), {Y}, true); setup_type("$allseq", pool(), {Y}, true); setup_type("$equiv", {A, B}, {Y}, true); + setup_type("$specify2", {EN, SRC, DST}, pool(), true); + setup_type("$specify3", {EN, SRC, DST, DAT}, pool(), true); } void setup_internals_eval() -- cgit v1.2.3 From e807e88b607834170692f56a5538b89fd4175a36 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:52:47 +0200 Subject: Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9e06b8323..4522b0a08 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1199,10 +1199,10 @@ namespace { param_bool("\\SRC_DST_PEN"); param_bool("\\SRC_DST_POL"); param("\\T_RISE_MIN"); - param("\\T_RISE_AVG"); + param("\\T_RISE_TYP"); param("\\T_RISE_MAX"); param("\\T_FALL_MIN"); - param("\\T_FALL_AVG"); + param("\\T_FALL_TYP"); param("\\T_FALL_MAX"); port("\\EN", 1); port("\\SRC", param("\\SRC_WIDTH")); -- cgit v1.2.3 From 71c38d9de527e1a8b55ba295df459fbcf2a0fe47 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 15:46:40 +0200 Subject: Add $specrule cells for $setup/$hold/$skew specify rules Signed-off-by: Clifford Wolf --- kernel/celltypes.h | 2 ++ kernel/rtlil.cc | 15 +++++++++++++++ 2 files changed, 17 insertions(+) (limited to 'kernel') diff --git a/kernel/celltypes.h b/kernel/celltypes.h index f8c73ed83..4e91eddda 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -86,6 +86,7 @@ struct CellTypes IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y"; IdString SRC = "\\SRC", DST = "\\DST", DAT = "\\DAT"; + IdString EN_SRC = "\\EN_SRC", EN_DST = "\\EN_DST"; setup_type("$tribuf", {A, EN}, {Y}, true); @@ -102,6 +103,7 @@ struct CellTypes setup_type("$equiv", {A, B}, {Y}, true); setup_type("$specify2", {EN, SRC, DST}, pool(), true); setup_type("$specify3", {EN, SRC, DST, DAT}, pool(), true); + setup_type("$specrule", {EN_SRC, EN_DST, SRC, DST}, pool(), true); } void setup_internals_eval() diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 4522b0a08..dae3698a9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1218,6 +1218,21 @@ namespace { return; } + if (cell->type == "$specrule") { + param_bool("\\SRC_PEN"); + param_bool("\\SRC_POL"); + param_bool("\\DST_PEN"); + param_bool("\\DST_POL"); + param_bool("\\LIMIT_GT"); + param("\\T_LIMIT"); + port("\\SRC_EN", 1); + port("\\DST_EN", 1); + port("\\SRC", param("\\SRC_WIDTH")); + port("\\DST", param("\\DST_WIDTH")); + check_expected(); + return; + } + if (cell->type == "$_BUF_") { check_gate("AY"); return; } if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } -- cgit v1.2.3 From 4575e4ad86494e99dd05200f7242dfa632053c78 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 22:18:04 +0200 Subject: Improve $specrule interface Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index dae3698a9..3dd18c296 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1223,7 +1223,8 @@ namespace { param_bool("\\SRC_POL"); param_bool("\\DST_PEN"); param_bool("\\DST_POL"); - param_bool("\\LIMIT_GT"); + param_bool("\\SKEW"); + param_bool("\\HOLD"); param("\\T_LIMIT"); port("\\SRC_EN", 1); port("\\DST_EN", 1); -- cgit v1.2.3 From 64925b4e8f7890f5447d9655b2c69dd59a93f7cd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 22:57:10 +0200 Subject: Improve $specrule interface Signed-off-by: Clifford Wolf --- kernel/rtlil.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'kernel') diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3dd18c296..040644c47 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1219,13 +1219,13 @@ namespace { } if (cell->type == "$specrule") { + param("\\TYPE"); param_bool("\\SRC_PEN"); param_bool("\\SRC_POL"); param_bool("\\DST_PEN"); param_bool("\\DST_POL"); - param_bool("\\SKEW"); - param_bool("\\HOLD"); param("\\T_LIMIT"); + param("\\T_LIMIT2"); port("\\SRC_EN", 1); port("\\DST_EN", 1); port("\\SRC", param("\\SRC_WIDTH")); -- cgit v1.2.3 From 87426f5a06b0cf9d1fe44efda65e3c048d89d322 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 4 May 2019 08:46:24 +0200 Subject: Improve write_verilog specify support Signed-off-by: Clifford Wolf --- kernel/rtlil.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'kernel') diff --git a/kernel/rtlil.h b/kernel/rtlil.h index db5c33c73..0c3fa6f76 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -50,7 +50,7 @@ namespace RTLIL CONST_FLAG_NONE = 0, CONST_FLAG_STRING = 1, CONST_FLAG_SIGNED = 2, // only used for parameters - CONST_FLAG_REAL = 4 // unused -- to be used for parameters + CONST_FLAG_REAL = 4 // only used for parameters }; struct Const; -- cgit v1.2.3