From d20e971725a780458ccd18d08be7ecfb67884eaf Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 1 Dec 2019 01:51:16 +0000 Subject: write_cxxrtl: new backend. This commit adds a basic implementation that isn't very performant but implements most of the planned features. --- kernel/yosys.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'kernel/yosys.h') diff --git a/kernel/yosys.h b/kernel/yosys.h index 16e0aaf1c..6aed7c96a 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -207,6 +207,7 @@ namespace RTLIL { struct SigSpec; struct Wire; struct Cell; + struct Memory; struct Module; struct Design; struct Monitor; @@ -229,6 +230,7 @@ using RTLIL::Design; namespace hashlib { template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; + template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; @@ -236,6 +238,7 @@ namespace hashlib { template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; + template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; template<> struct hash_ops : hash_obj_ops {}; -- cgit v1.2.3