From c38283dbd033ba95554600bbaa850de707ab2a78 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 17:48:41 +0200 Subject: Small bug fixes in $not, $neg, and $shiftx models --- kernel/satgen.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'kernel/satgen.h') diff --git a/kernel/satgen.h b/kernel/satgen.h index beb037686..3685cd6e6 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -357,7 +357,7 @@ struct SatGen if (model_undef) { std::vector undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep); std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); - extendSignalWidthUnary(undef_a, undef_y, cell, true); + extendSignalWidthUnary(undef_a, undef_y, cell, false); ez->assume(ez->vec_eq(undef_a, undef_y)); undefGating(y, yy, undef_y); } @@ -671,7 +671,7 @@ struct SatGen int extend_bit = ez->FALSE; - if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool()) + if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool()) extend_bit = a.back(); while (y.size() < a.size()) @@ -703,7 +703,8 @@ struct SatGen std::vector undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep); std::vector undef_a_shifted; - if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool()) + extend_bit = cell->type == "$shiftx" ? ez->TRUE : ez->FALSE; + if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool()) extend_bit = undef_a.back(); while (undef_y.size() < undef_a.size()) -- cgit v1.2.3