From d963e8c2c6207ad98d48dc528922ad58c030173f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Sep 2019 17:00:19 -0700
Subject: Fix typo

---
 kernel/rtlil.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'kernel/rtlil.cc')

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 17be28f78..ded1cd60e 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
 {
 	std::vector<RTLIL::Cell*> result;
-	result.reserve(wires_.size());
+	result.reserve(cells_.size());
 	for (auto &it : cells_)
 		if (design->selected(this, it.second))
 			result.push_back(it.second);
-- 
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