From c7076495f197732725456992c9a02aed9966139a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 22 May 2021 16:36:50 +0200
Subject: kernel/mem: Add a check() function.

---
 kernel/mem.cc | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

(limited to 'kernel/mem.cc')

diff --git a/kernel/mem.cc b/kernel/mem.cc
index 9d68dbbb7..7d20833e5 100644
--- a/kernel/mem.cc
+++ b/kernel/mem.cc
@@ -52,6 +52,7 @@ void Mem::remove() {
 }
 
 void Mem::emit() {
+	check();
 	std::vector<int> rd_left;
 	for (int i = 0; i < GetSize(rd_ports); i++) {
 		auto &port = rd_ports[i];
@@ -257,6 +258,27 @@ Const Mem::get_init_data() const {
 	return init_data;
 }
 
+void Mem::check() {
+	for (auto &port : rd_ports) {
+		if (port.removed)
+			continue;
+		log_assert(GetSize(port.clk) == 1);
+		log_assert(GetSize(port.en) == 1);
+		log_assert(GetSize(port.data) == width);
+		if (!port.clk_enable) {
+			log_assert(!port.transparent);
+		}
+	}
+	for (int i = 0; i < GetSize(wr_ports); i++) {
+		auto &port = wr_ports[i];
+		if (port.removed)
+			continue;
+		log_assert(GetSize(port.clk) == 1);
+		log_assert(GetSize(port.en) == width);
+		log_assert(GetSize(port.data) == width);
+	}
+}
+
 namespace {
 
 	struct MemIndex {
@@ -333,6 +355,7 @@ namespace {
 			for (auto &it : inits)
 				res.inits.push_back(it.second);
 		}
+		res.check();
 		return res;
 	}
 
@@ -389,6 +412,7 @@ namespace {
 			mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, res.width);
 			res.wr_ports.push_back(mwr);
 		}
+		res.check();
 		return res;
 	}
 
@@ -451,6 +475,7 @@ Cell *Mem::extract_rdff(int idx) {
 	port.clk = State::S0;
 	port.clk_enable = false;
 	port.clk_polarity = true;
+	port.transparent = false;
 
 	return c;
 }
-- 
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