From a6c96b986be313368b4fa03eba5cf6987448100c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 26 Dec 2014 10:53:21 +0100
Subject: Added Yosys::{dict,nodict,vector} container types

---
 frontends/ast/ast.cc           | 2 +-
 frontends/ast/ast.h            | 2 +-
 frontends/ilang/ilang_parser.y | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'frontends')

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 56ea64eff..0f79352f7 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1018,7 +1018,7 @@ AstModule::~AstModule()
 }
 
 // create a new parametric module (when needed) and return the name of the generated module
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters)
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters)
 {
 	std::string stripped_name = name.str();
 
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 023755387..27cf0ef3d 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -268,7 +268,7 @@ namespace AST
 		AstNode *ast;
 		bool nolatches, nomem2reg, mem2reg, lib, noopt, icells, autowire;
 		virtual ~AstModule();
-		virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
+		virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters);
 		virtual RTLIL::Module *clone() const;
 	};
 
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index a5cc06898..4e0981b51 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -36,7 +36,7 @@ namespace ILANG_FRONTEND {
 	RTLIL::Process *current_process;
 	std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
 	std::vector<RTLIL::CaseRule*> case_stack;
-	std::map<RTLIL::IdString, RTLIL::Const> attrbuf;
+	dict<RTLIL::IdString, RTLIL::Const> attrbuf;
 }
 using namespace ILANG_FRONTEND;
 YOSYS_NAMESPACE_END
-- 
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