From 98c4feb72ff52f12aadd34b0deccb819d701ff2c Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Thu, 4 Feb 2021 12:12:59 +0100 Subject: Add check of begin/end labels for genblock Signed-off-by: Kamil Rakoczy --- frontends/verilog/verilog_parser.y | 2 ++ 1 file changed, 2 insertions(+) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 6255a4204..fb5846f7b 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2794,6 +2794,8 @@ gen_block: ast_stack.push_back(node); } module_gen_body TOK_END opt_label { exitTypeScope(); + if ($3 != NULL && $7 != NULL && *$3 != *$7) + frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1); delete $3; delete $7; SET_AST_NODE_LOC(ast_stack.back(), @1, @7); -- cgit v1.2.3