From 323aa1df75dcc21e94c4dfbdb77eaad40f48d081 Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Wed, 6 May 2020 07:22:17 +0000 Subject: verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace. --- frontends/verilog/verilog_lexer.l | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index f6a3ac4db..63c0ba159 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -48,16 +48,18 @@ USING_YOSYS_NAMESPACE using namespace AST; using namespace VERILOG_FRONTEND; +#define YYSTYPE FRONTEND_VERILOG_YYSTYPE +#define YYLTYPE FRONTEND_VERILOG_YYLTYPE + YOSYS_NAMESPACE_BEGIN namespace VERILOG_FRONTEND { std::vector fn_stack; std::vector ln_stack; + YYLTYPE real_location; + YYLTYPE old_location; } YOSYS_NAMESPACE_END -#define YYSTYPE FRONTEND_VERILOG_YYSTYPE -#define YYLTYPE FRONTEND_VERILOG_YYLTYPE - #define SV_KEYWORD(_tok) \ if (sv_mode) return _tok; \ log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\ @@ -73,9 +75,6 @@ YOSYS_NAMESPACE_END #define YY_INPUT(buf,result,max_size) \ result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size) -YYLTYPE real_location; -YYLTYPE old_location; - #define YY_USER_ACTION \ old_location = real_location; \ real_location.first_line = real_location.last_line; \ -- cgit v1.2.3 From 1f3003be7d464372b1c94d6b8e47ffa0d75de0d3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 13:00:36 -0700 Subject: verilog: error out when non-ANSI task/func arguments --- frontends/verilog/verilog_parser.y | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index db9a130cf..b7c6af91e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -853,7 +853,11 @@ task_func_port: } if (astbuf2 && astbuf2->children.size() != 2) frontend_verilog_yyerror("task/function argument range must be of the form: [:], [+:], or [-:]"); - } wire_name | wire_name; + } wire_name | + { + if (!astbuf1) + frontend_verilog_yyerror("Non-ANSI style task/function arguments not currently supported"); + } wire_name; task_func_body: task_func_body behavioral_stmt | -- cgit v1.2.3 From 237962debd9fcb7e9fb45f53bc8a53f0c34d9888 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 May 2020 13:33:37 -0700 Subject: verilog: default to input in sv mode if task/func has no dir ... otherwise error --- frontends/verilog/verilog_parser.y | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index b7c6af91e..f250d7685 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -855,8 +855,16 @@ task_func_port: frontend_verilog_yyerror("task/function argument range must be of the form: [:], [+:], or [-:]"); } wire_name | { - if (!astbuf1) - frontend_verilog_yyerror("Non-ANSI style task/function arguments not currently supported"); + if (!astbuf1) { + if (!sv_mode) + frontend_verilog_yyerror("task/function argument direction missing"); + albuf = new dict; + astbuf1 = new AstNode(AST_WIRE); + current_wire_rand = false; + current_wire_const = false; + astbuf1->is_input = true; + astbuf2 = NULL; + } } wire_name; task_func_body: -- cgit v1.2.3 From 7101ef550ba4b215d41fc82e52e3aa714afcbdbe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 16:10:11 -0700 Subject: verilog: attributes before task enable (but 13 s/r conflicts) --- frontends/verilog/verilog_parser.y | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index db9a130cf..fd4ff68a9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2217,23 +2217,23 @@ behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | simple_behavioral_stmt ';' | ';' | - hierarchical_id attr { + attr hierarchical_id { AstNode *node = new AstNode(AST_TCALL); - node->str = *$1; - delete $1; + node->str = *$2; + delete $2; ast_stack.back()->children.push_back(node); ast_stack.push_back(node); - append_attr(node, $2); + append_attr(node, $1); } opt_arg_list ';'{ ast_stack.pop_back(); } | - TOK_MSG_TASKS attr { + attr TOK_MSG_TASKS { AstNode *node = new AstNode(AST_TCALL); - node->str = *$1; - delete $1; + node->str = *$2; + delete $2; ast_stack.back()->children.push_back(node); ast_stack.push_back(node); - append_attr(node, $2); + append_attr(node, $1); } opt_arg_list ';'{ ast_stack.pop_back(); } | @@ -2330,8 +2330,6 @@ behavioral_stmt: ast_stack.pop_back(); }; - ; - unique_case_attr: /* empty */ { $$ = false; -- cgit v1.2.3 From 38e858af8d5f61677d9686c022c864857f729d58 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 May 2020 09:10:56 -0700 Subject: Update frontends/verilog/verilog_parser.y Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com> --- frontends/verilog/verilog_parser.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index fd4ff68a9..ae7a3f4aa 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2216,7 +2216,7 @@ simple_behavioral_stmt: behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | - simple_behavioral_stmt ';' | ';' | + attr simple_behavioral_stmt ';' | ';' | attr hierarchical_id { AstNode *node = new AstNode(AST_TCALL); node->str = *$2; -- cgit v1.2.3 From d21a07c7b5ef57de5428e5f7913338af582146b5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 09:33:19 -0700 Subject: verilog: fix #2037 by permitting (and freeing) attributes on null stmt --- frontends/verilog/verilog_parser.y | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d39b72547..a0250439e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2228,7 +2228,11 @@ simple_behavioral_stmt: behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | - attr simple_behavioral_stmt ';' | ';' | + attr simple_behavioral_stmt ';' | + attr ';' { + log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n"); + free_attr($1); + } | attr hierarchical_id { AstNode *node = new AstNode(AST_TCALL); node->str = *$2; -- cgit v1.2.3 From 88bddb37c91e8fe136e5c9cc2ade20fadccd1946 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 10:20:33 -0700 Subject: verilog: handle empty generate statement by removing gen_stmt_or_null... ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay. --- frontends/verilog/verilog_parser.y | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index a0250439e..eb7e136ae 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2440,7 +2440,7 @@ gen_case_item: } case_select { case_type_stack.push_back(0); SET_AST_NODE_LOC(ast_stack.back(), @2, @2); - } gen_stmt_or_null { + } gen_stmt_block { case_type_stack.pop_back(); ast_stack.pop_back(); }; @@ -2532,7 +2532,11 @@ module_gen_body: /* empty */; gen_stmt_or_module_body_stmt: - gen_stmt | module_body_stmt; + gen_stmt | module_body_stmt | + attr ';' { + log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n"); + free_attr($1); + }; // this production creates the obligatory if-else shift/reduce conflict gen_stmt: @@ -2554,7 +2558,7 @@ gen_stmt: AstNode *block = new AstNode(AST_GENBLOCK); ast_stack.back()->children.push_back(block); ast_stack.push_back(block); - } gen_stmt_or_null { + } gen_stmt_block { ast_stack.pop_back(); } opt_gen_else { SET_AST_NODE_LOC(ast_stack.back(), @1, @7); @@ -2604,11 +2608,8 @@ gen_stmt_block: ast_stack.pop_back(); }; -gen_stmt_or_null: - gen_stmt_block | ';'; - opt_gen_else: - TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN; + TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN; expr: basic_expr { -- cgit v1.2.3 From 1c117ac0236517d0d7150dcc8d1fed19288bd692 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 10:46:40 -0700 Subject: verilog: do not warn for attributes on null statements --- frontends/verilog/verilog_parser.y | 2 -- 1 file changed, 2 deletions(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index eb7e136ae..475557af9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2230,7 +2230,6 @@ behavioral_stmt: non_opt_delay behavioral_stmt | attr simple_behavioral_stmt ';' | attr ';' { - log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n"); free_attr($1); } | attr hierarchical_id { @@ -2534,7 +2533,6 @@ module_gen_body: gen_stmt_or_module_body_stmt: gen_stmt | module_body_stmt | attr ';' { - log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n"); free_attr($1); }; -- cgit v1.2.3 From c5a9abba11a2e69a5e9944c179f7dba3d24f417a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 May 2020 09:46:26 -0700 Subject: verilog: move attr from simple_behav_stmt to its children to attach --- frontends/verilog/verilog_parser.y | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 475557af9..c8223f41d 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2203,32 +2203,36 @@ assert_property: }; simple_behavioral_stmt: - lvalue '=' delay expr { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4); + attr lvalue '=' delay expr { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $5); ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @1, @4); + SET_AST_NODE_LOC(node, @2, @5); + append_attr(node, $1); } | - lvalue TOK_INCREMENT { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true))); + attr lvalue TOK_INCREMENT { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true))); ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @1, @2); + SET_AST_NODE_LOC(node, @2, @3); + append_attr(node, $1); } | - lvalue TOK_DECREMENT { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true))); + attr lvalue TOK_DECREMENT { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true))); ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @1, @2); + SET_AST_NODE_LOC(node, @2, @3); + append_attr(node, $1); } | - lvalue OP_LE delay expr { - AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4); + attr lvalue OP_LE delay expr { + AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5); ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @1, @4); + SET_AST_NODE_LOC(node, @2, @5); + append_attr(node, $1); }; // this production creates the obligatory if-else shift/reduce conflict behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | - attr simple_behavioral_stmt ';' | + simple_behavioral_stmt ';' | attr ';' { free_attr($1); } | -- cgit v1.2.3 From 6aa0f72ae9e47c81441a2cecef18b7f90671ec6d Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Fri, 22 May 2020 14:29:42 +0100 Subject: Silence spurious warning in Verilog lexer when compiling with GCC The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL. --- frontends/verilog/verilog_lexer.l | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'frontends/verilog') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index f6a3ac4db..65a2e9a78 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -128,7 +128,9 @@ static bool isUserType(std::string &s) %x BASED_CONST %% - int comment_caller; + // Initialise comment_caller to something to avoid a "maybe undefined" + // warning from GCC. + int comment_caller = INITIAL; "`file_push "[^\n]* { fn_stack.push_back(current_filename); -- cgit v1.2.3