From 8f9bba1bbfdb56630dadd75a3f92f7bfb26b3df6 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Mon, 4 May 2020 20:22:16 -0400 Subject: verilog: allow null gen-if then block --- frontends/verilog/verilog_parser.y | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4a5aba79e..3738f8f3d 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2533,7 +2533,12 @@ gen_stmt: ast_stack.back()->children.push_back(node); ast_stack.push_back(node); ast_stack.back()->children.push_back($3); - } gen_stmt_block opt_gen_else { + AstNode *block = new AstNode(AST_GENBLOCK); + ast_stack.back()->children.push_back(block); + ast_stack.push_back(block); + } gen_stmt_or_null { + ast_stack.pop_back(); + } opt_gen_else { SET_AST_NODE_LOC(ast_stack.back(), @1, @7); ast_stack.pop_back(); } | -- cgit v1.2.3