From 8f8baccfde62d238025024eb1060ae0aba4c77e3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 7 Jun 2017 12:30:24 +0200
Subject: Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and
 "rand const reg"

---
 frontends/verilog/verilog_parser.y | 1 +
 1 file changed, 1 insertion(+)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 154b59ebc..c5ff3d402 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -764,6 +764,7 @@ wire_name_and_opt_assign:
 			AstNode *fcall = new AstNode(AST_FCALL);
 			wire->str = ast_stack.back()->children.back()->str;
 			fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
+			fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
 			ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
 		}
 	} |
-- 
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