From 52cbf1bea52b05c3fa57712ce201369c92400008 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Fri, 6 Aug 2021 20:49:41 +0200
Subject: verilog: Support tri/triand/trior wire types.

These are, by the standard, just aliases for wire/wand/wor.

Fixes #2918.
---
 frontends/verilog/verilog_lexer.l | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'frontends/verilog/verilog_lexer.l')

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 54fb65240..0306f5494 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -277,8 +277,11 @@ static bool isUserType(std::string &s)
 "output"  { return TOK_OUTPUT; }
 "inout"   { return TOK_INOUT; }
 "wire"    { return TOK_WIRE; }
+"tri"     { return TOK_WIRE; }
 "wor"     { return TOK_WOR; }
+"trior"   { return TOK_WOR; }
 "wand"    { return TOK_WAND; }
+"triand"  { return TOK_WAND; }
 "reg"     { return TOK_REG; }
 "integer" { return TOK_INTEGER; }
 "signed"  { return TOK_SIGNED; }
-- 
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