From 3cc95fb4be27a3e130563db102ed268876027288 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Apr 2019 21:58:57 +0200 Subject: Add specify parser Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_lexer.l | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 6ef38252a..b73ccf5c1 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -148,7 +148,7 @@ YOSYS_NAMESPACE_END "endfunction" { return TOK_ENDFUNCTION; } "task" { return TOK_TASK; } "endtask" { return TOK_ENDTASK; } -"specify" { return TOK_SPECIFY; } +"specify" { return specify_mode ? TOK_SPECIFY : TOK_IGNORED_SPECIFY; } "endspecify" { return TOK_ENDSPECIFY; } "specparam" { return TOK_SPECPARAM; } "package" { SV_KEYWORD(TOK_PACKAGE); } @@ -411,6 +411,11 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { "+:" { return TOK_POS_INDEXED; } "-:" { return TOK_NEG_INDEXED; } +[-+]?[=*]> { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_SPECIFY_OPER; +} + "/*" { BEGIN(COMMENT); } . /* ignore comment body */ \n /* ignore comment body */ -- cgit v1.2.3 From 41b843c27b486ef4b3c0044fbb00b161faaf89d9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Apr 2019 22:58:51 +0200 Subject: Un-break default specify parser Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_lexer.l | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index b73ccf5c1..f49f9d3a2 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -412,6 +412,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { "-:" { return TOK_NEG_INDEXED; } [-+]?[=*]> { + if (!specify_mode) REJECT; frontend_verilog_yylval.string = new std::string(yytext); return TOK_SPECIFY_OPER; } -- cgit v1.2.3 From 71c38d9de527e1a8b55ba295df459fbcf2a0fe47 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 15:46:40 +0200 Subject: Add $specrule cells for $setup/$hold/$skew specify rules Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_lexer.l | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index f49f9d3a2..cd96236a1 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -301,6 +301,12 @@ supply1 { return TOK_SUPPLY1; } return TOK_ID; } +"$"(setup|hold|skew) { + if (!specify_mode) REJECT; + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_ID; +} + "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } @@ -417,6 +423,11 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { return TOK_SPECIFY_OPER; } +"&&&" { + if (!specify_mode) REJECT; + return TOK_SPECIFY_AND; +} + "/*" { BEGIN(COMMENT); } . /* ignore comment body */ \n /* ignore comment body */ -- cgit v1.2.3 From 64925b4e8f7890f5447d9655b2c69dd59a93f7cd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 22:57:10 +0200 Subject: Improve $specrule interface Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_lexer.l | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index cd96236a1..1a818a2ce 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -301,7 +301,7 @@ supply1 { return TOK_SUPPLY1; } return TOK_ID; } -"$"(setup|hold|skew) { +"$"(setup|hold|setuphold|removal|recovery|recrem|skew|timeskew|fullskew|nochange) { if (!specify_mode) REJECT; frontend_verilog_yylval.string = new std::string(yytext); return TOK_ID; -- cgit v1.2.3 From 9804c86e87ec83edd29d224f01311b6ae1d41181 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 4 May 2019 07:52:51 +0200 Subject: Add approximate support for SV "var" keyword, fixes #987 Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_lexer.l | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 6ef38252a..59ef3e36e 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -207,6 +207,7 @@ YOSYS_NAMESPACE_END "checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); } "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); } "logic" { SV_KEYWORD(TOK_LOGIC); } +"var" { SV_KEYWORD(TOK_VAR); } "bit" { SV_KEYWORD(TOK_REG); } "eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } -- cgit v1.2.3 From 66d6ca2de2e31d7c0460ae314b61136e42ded8c5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 4 May 2019 09:25:32 +0200 Subject: Add support for SVA "final" keyword Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_lexer.l | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 6ef38252a..e97632663 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -206,6 +206,7 @@ YOSYS_NAMESPACE_END "const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); } "checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); } "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); } +"final" { SV_KEYWORD(TOK_FINAL); } "logic" { SV_KEYWORD(TOK_LOGIC); } "bit" { SV_KEYWORD(TOK_REG); } -- cgit v1.2.3