From 41b843c27b486ef4b3c0044fbb00b161faaf89d9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Apr 2019 22:58:51 +0200 Subject: Un-break default specify parser Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_lexer.l | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index b73ccf5c1..f49f9d3a2 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -412,6 +412,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { "-:" { return TOK_NEG_INDEXED; } [-+]?[=*]> { + if (!specify_mode) REJECT; frontend_verilog_yylval.string = new std::string(yytext); return TOK_SPECIFY_OPER; } -- cgit v1.2.3