From 007bdff55d69e6e29091c7beff19c36eeb7ed078 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 12 Feb 2014 23:29:54 +0100
Subject: Added support for functions returning integer

---
 frontends/verilog/parser.y | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 5b6bf58c2..8080729b0 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -106,7 +106,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT
 
-%type <ast> wire_type range non_opt_range expr basic_expr concat_list rvalue lvalue lvalue_concat_list
+%type <ast> wire_type range non_opt_range range_or_integer expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 %type <string> opt_label tok_prim_wrapper hierarchical_id
 %type <boolean> opt_signed
 %type <al> attr
@@ -360,6 +360,16 @@ range:
 		$$ = NULL;
 	};
 
+range_or_integer:
+	range {
+		$$ = $1;
+	} |
+	TOK_INTEGER {
+		$$ = new AstNode(AST_RANGE);
+		$$->children.push_back(AstNode::mkconst_int(31, true));
+		$$->children.push_back(AstNode::mkconst_int(0, true));
+	};
+
 module_body:
 	module_body module_body_stmt |
 	/* empty */;
@@ -380,7 +390,7 @@ task_func_decl:
 		current_function_or_task = NULL;
 		ast_stack.pop_back();
 	} |
-	TOK_FUNCTION opt_signed range TOK_ID ';' {
+	TOK_FUNCTION opt_signed range_or_integer TOK_ID ';' {
 		current_function_or_task = new AstNode(AST_FUNCTION);
 		current_function_or_task->str = *$4;
 		ast_stack.back()->children.push_back(current_function_or_task);
-- 
cgit v1.2.3


From 02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 17 Feb 2014 14:28:52 +0100
Subject: Added Verilog support for "`default_nettype none"

---
 frontends/verilog/parser.y | 1 +
 1 file changed, 1 insertion(+)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 8080729b0..4726f1aa3 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -53,6 +53,7 @@ namespace VERILOG_FRONTEND {
 	struct AstNode *current_ast, *current_ast_mod;
 	int current_function_or_task_port_id;
 	std::vector<char> case_type_stack;
+	bool default_nettype_wire;
 }
 
 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
-- 
cgit v1.2.3


From a1be4816d602548f4454242dc17f8a85ccaa91bd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 20 Apr 2014 14:22:11 +0200
Subject: Replaced depricated %name-prefix= bison directive

---
 frontends/verilog/parser.y | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 4726f1aa3..ed9be692b 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -84,7 +84,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 
 %}
 
-%name-prefix="frontend_verilog_yy"
+%name-prefix "frontend_verilog_yy"
 
 %union {
 	std::string *string;
-- 
cgit v1.2.3


From b5cd7a01793294a53d91a2cd3ee9bbca5b9a8c54 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 6 Jun 2014 17:40:04 +0200
Subject: added while and repeat support to verilog parser

---
 frontends/verilog/parser.y | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index ed9be692b..a12dcf142 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -98,7 +98,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
-%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR
+%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
 %token TOK_POSEDGE TOK_NEGEDGE TOK_OR
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK
@@ -819,6 +819,32 @@ behavioral_stmt:
 		ast_stack.pop_back();
 		ast_stack.pop_back();
 	} |
+	attr TOK_WHILE '(' expr ')' {
+		AstNode *node = new AstNode(AST_WHILE);
+		ast_stack.back()->children.push_back(node);
+		ast_stack.push_back(node);
+		append_attr(node, $1);
+		AstNode *block = new AstNode(AST_BLOCK);
+		ast_stack.back()->children.push_back($4);
+		ast_stack.back()->children.push_back(block);
+		ast_stack.push_back(block);
+	} behavioral_stmt {
+		ast_stack.pop_back();
+		ast_stack.pop_back();
+	} |
+	attr TOK_REPEAT '(' expr ')' {
+		AstNode *node = new AstNode(AST_REPEAT);
+		ast_stack.back()->children.push_back(node);
+		ast_stack.push_back(node);
+		append_attr(node, $1);
+		AstNode *block = new AstNode(AST_BLOCK);
+		ast_stack.back()->children.push_back($4);
+		ast_stack.back()->children.push_back(block);
+		ast_stack.push_back(block);
+	} behavioral_stmt {
+		ast_stack.pop_back();
+		ast_stack.pop_back();
+	} |
 	attr TOK_IF '(' expr ')' {
 		AstNode *node = new AstNode(AST_CASE);
 		AstNode *block = new AstNode(AST_BLOCK);
-- 
cgit v1.2.3


From 5281562d0e9468c584e6db6f30908e3155a76ad2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 6 Jun 2014 23:05:01 +0200
Subject: made the generate..endgenrate keywords optional

---
 frontends/verilog/parser.y | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index a12dcf142..42a8f91c5 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -373,6 +373,8 @@ range_or_integer:
 
 module_body:
 	module_body module_body_stmt |
+	/* the following line makes the generate..endgenrate keywords optional */
+	module_body gen_stmt |
 	/* empty */;
 
 module_body_stmt:
@@ -1013,9 +1015,12 @@ single_arg:
 	};
 
 module_gen_body:
-	module_gen_body gen_stmt |
+	module_gen_body gen_stmt_or_module_body_stmt |
 	/* empty */;
 
+gen_stmt_or_module_body_stmt:
+	gen_stmt | module_body_stmt;
+
 // this production creates the obligatory if-else shift/reduce conflict
 gen_stmt:
 	TOK_FOR '(' {
@@ -1054,15 +1059,14 @@ gen_stmt:
 		if ($6 != NULL)
 			delete $6;
 		ast_stack.pop_back();
-	} |
-	module_body_stmt;
+	};
 
 gen_stmt_block:
 	{
 		AstNode *node = new AstNode(AST_GENBLOCK);
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
-	} gen_stmt {
+	} gen_stmt_or_module_body_stmt {
 		ast_stack.pop_back();
 	};
 
-- 
cgit v1.2.3


From e275e8eef9ae47670075bd73a671f3acd3c0ca52 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 7 Jun 2014 11:48:50 +0200
Subject: Add support for cell arrays

---
 frontends/verilog/parser.y | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 42a8f91c5..f422258c7 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -634,6 +634,13 @@ single_cell:
 			astbuf2->str = *$1;
 		delete $1;
 		ast_stack.back()->children.push_back(astbuf2);
+	} '(' cell_port_list ')' |
+	TOK_ID non_opt_range {
+		astbuf2 = astbuf1->clone();
+		if (astbuf2->type != AST_PRIMITIVE)
+			astbuf2->str = *$1;
+		delete $1;
+		ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
 	} '(' cell_port_list ')';
 
 prim_list:
-- 
cgit v1.2.3


From 482d9208aa9dacb7afe21f08c882d4881581013a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 12 Jun 2014 11:54:20 +0200
Subject: Added read_verilog -sv options, added support for bit, logic,
 allways_ff, always_comb, and always_latch

---
 frontends/verilog/parser.y | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index f422258c7..cce8a8c40 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -54,6 +54,7 @@ namespace VERILOG_FRONTEND {
 	int current_function_or_task_port_id;
 	std::vector<char> case_type_stack;
 	bool default_nettype_wire;
+	bool sv_mode;
 }
 
 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
@@ -105,7 +106,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
-%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT
+%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_PROPERTY
 
 %type <ast> wire_type range non_opt_range range_or_integer expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 %type <string> opt_label tok_prim_wrapper hierarchical_id
@@ -379,7 +380,7 @@ module_body:
 
 module_body_stmt:
 	task_func_decl | param_decl | localparam_decl | defparam_decl | wire_decl | assign_stmt | cell_stmt |
-	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert;
+	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property;
 
 task_func_decl:
 	TOK_TASK TOK_ID ';' {
@@ -773,6 +774,11 @@ assert:
 		ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $3));
 	};
 
+assert_property:
+	TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_ASSERT, $4));
+	};
+
 simple_behavioral_stmt:
 	lvalue '=' expr {
 		AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $3);
-- 
cgit v1.2.3


From 7ef0da32cdcddb50de8ba8acf0c6421fe5732c55 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 13 Jun 2014 11:29:23 +0200
Subject: Added Verilog lexer and parser support for real values

---
 frontends/verilog/parser.y | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index cce8a8c40..e51712b3f 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -35,7 +35,7 @@
 
 %{
 #include <list>
-#include <assert.h>
+#include <string.h>
 #include "verilog_frontend.h"
 #include "kernel/log.h"
 
@@ -94,7 +94,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 	bool boolean;
 }
 
-%token <string> TOK_STRING TOK_ID TOK_CONST TOK_PRIMITIVE
+%token <string> TOK_STRING TOK_ID TOK_CONST TOK_REAL TOK_PRIMITIVE
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
@@ -221,7 +221,7 @@ module:
 			frontend_verilog_yyerror("Missing details for module port `%s'.",
 					port_stubs.begin()->first.c_str());
 		ast_stack.pop_back();
-		assert(ast_stack.size() == 0);
+		log_assert(ast_stack.size() == 0);
 	};
 
 module_para_opt:
@@ -1133,6 +1133,17 @@ basic_expr:
 			log_error("Value conversion failed: `%s'\n", $1->c_str());
 		delete $1;
 	} |
+	TOK_REAL {
+		$$ = new AstNode(AST_REALVALUE);
+		char *p = strdup($1->c_str()), *q;
+		for (int i = 0, j = 0; !p[j]; j++)
+			if (p[j] != '_')
+				p[i++] = p[j], p[i] = 0;
+		$$->realvalue = strtod(p, &q);
+		log_assert(*q == 0);
+		delete $1;
+		free(p);
+	} |
 	TOK_STRING {
 		$$ = AstNode::mkconst_str(*$1);
 		delete $1;
-- 
cgit v1.2.3


From 9bd7d5c46856f25fd7befcdfe20198fd8eb59ccd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 14 Jun 2014 12:00:47 +0200
Subject: Added handling of real-valued parameters/localparams

---
 frontends/verilog/parser.y | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index e51712b3f..57defd56b 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -94,7 +94,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 	bool boolean;
 }
 
-%token <string> TOK_STRING TOK_ID TOK_CONST TOK_REAL TOK_PRIMITIVE
+%token <string> TOK_STRING TOK_ID TOK_CONST TOK_REALVAL TOK_PRIMITIVE
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
@@ -103,7 +103,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_POSEDGE TOK_NEGEDGE TOK_OR
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK
-%token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR
+%token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_PROPERTY
@@ -438,6 +438,13 @@ param_integer:
 		astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
 	} | /* empty */;
 
+param_real:
+	TOK_REAL {
+		if (astbuf1->children.size() != 1)
+			frontend_verilog_yyerror("Syntax error.");
+		astbuf1->children.push_back(new AstNode(AST_REALVALUE));
+	} | /* empty */;
+
 param_range:
 	range {
 		if ($1 != NULL) {
@@ -451,7 +458,7 @@ param_decl:
 	TOK_PARAMETER {
 		astbuf1 = new AstNode(AST_PARAMETER);
 		astbuf1->children.push_back(AstNode::mkconst_int(0, true));
-	} param_signed param_integer param_range param_decl_list ';' {
+	} param_signed param_integer param_real param_range param_decl_list ';' {
 		delete astbuf1;
 	};
 
@@ -459,7 +466,7 @@ localparam_decl:
 	TOK_LOCALPARAM {
 		astbuf1 = new AstNode(AST_LOCALPARAM);
 		astbuf1->children.push_back(AstNode::mkconst_int(0, true));
-	} param_signed param_integer param_range param_decl_list ';' {
+	} param_signed param_integer param_real param_range param_decl_list ';' {
 		delete astbuf1;
 	};
 
@@ -1133,7 +1140,7 @@ basic_expr:
 			log_error("Value conversion failed: `%s'\n", $1->c_str());
 		delete $1;
 	} |
-	TOK_REAL {
+	TOK_REALVAL {
 		$$ = new AstNode(AST_REALVALUE);
 		char *p = strdup($1->c_str()), *q;
 		for (int i = 0, j = 0; !p[j]; j++)
-- 
cgit v1.2.3


From 0c4c79c4c6f8a433ef4b141b1523bccc261f8231 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 16 Jun 2014 15:02:40 +0200
Subject: Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)

---
 frontends/verilog/parser.y | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 57defd56b..37c3232aa 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -108,7 +108,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_PROPERTY
 
-%type <ast> wire_type range non_opt_range range_or_integer expr basic_expr concat_list rvalue lvalue lvalue_concat_list
+%type <ast> wire_type range non_opt_range range_or_signed_int expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 %type <string> opt_label tok_prim_wrapper hierarchical_id
 %type <boolean> opt_signed
 %type <al> attr
@@ -322,6 +322,7 @@ wire_type_token:
 		astbuf3->is_reg = true;
 		astbuf3->range_left = 31;
 		astbuf3->range_right = 0;
+		astbuf3->is_signed = true;
 	} |
 	TOK_GENVAR {
 		astbuf3->type = AST_GENVAR;
@@ -362,7 +363,7 @@ range:
 		$$ = NULL;
 	};
 
-range_or_integer:
+range_or_signed_int:
 	range {
 		$$ = $1;
 	} |
@@ -370,6 +371,7 @@ range_or_integer:
 		$$ = new AstNode(AST_RANGE);
 		$$->children.push_back(AstNode::mkconst_int(31, true));
 		$$->children.push_back(AstNode::mkconst_int(0, true));
+		$$->is_signed = true;
 	};
 
 module_body:
@@ -394,16 +396,19 @@ task_func_decl:
 		current_function_or_task = NULL;
 		ast_stack.pop_back();
 	} |
-	TOK_FUNCTION opt_signed range_or_integer TOK_ID ';' {
+	TOK_FUNCTION opt_signed range_or_signed_int TOK_ID ';' {
 		current_function_or_task = new AstNode(AST_FUNCTION);
 		current_function_or_task->str = *$4;
 		ast_stack.back()->children.push_back(current_function_or_task);
 		ast_stack.push_back(current_function_or_task);
 		AstNode *outreg = new AstNode(AST_WIRE);
-		if ($3 != NULL)
-			outreg->children.push_back($3);
 		outreg->str = *$4;
 		outreg->is_signed = $2;
+		if ($3 != NULL) {
+			outreg->children.push_back($3);
+			outreg->is_signed = $2 || $3->is_signed;
+			$3->is_signed = false;
+		}
 		current_function_or_task->children.push_back(outreg);
 		current_function_or_task_port_id = 1;
 		delete $4;
@@ -436,6 +441,7 @@ param_integer:
 		astbuf1->children.push_back(new AstNode(AST_RANGE));
 		astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
 		astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
+		astbuf1->is_signed = true;
 	} | /* empty */;
 
 param_real:
-- 
cgit v1.2.3


From ee8ad72fd950e1ee204e5c97155a50b8b1445dec Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 2 Jul 2014 06:27:04 +0200
Subject: fixed parsing of constant with comment between size and value

---
 frontends/verilog/parser.y | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 37c3232aa..ce7b99272 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -1140,6 +1140,13 @@ basic_expr:
 		delete $1;
 		delete $2;
 	} |
+	TOK_CONST TOK_CONST {
+		$$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
+		if ($$ == NULL || (*$2)[0] != '\'')
+			log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str());
+		delete $1;
+		delete $2;
+	} |
 	TOK_CONST {
 		$$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
 		if ($$ == NULL)
-- 
cgit v1.2.3


From 1cb25c05b37b0172dbc50e140fe20f25d973dd8a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 31 Jul 2014 13:19:47 +0200
Subject: Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

---
 frontends/verilog/parser.y | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index ce7b99272..c62e761e2 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -39,9 +39,11 @@
 #include "verilog_frontend.h"
 #include "kernel/log.h"
 
+USING_YOSYS_NAMESPACE
 using namespace AST;
 using namespace VERILOG_FRONTEND;
 
+YOSYS_NAMESPACE_BEGIN
 namespace VERILOG_FRONTEND {
 	int port_counter;
 	std::map<std::string, int> port_stubs;
@@ -56,6 +58,7 @@ namespace VERILOG_FRONTEND {
 	bool default_nettype_wire;
 	bool sv_mode;
 }
+YOSYS_NAMESPACE_END
 
 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
 {
@@ -89,8 +92,8 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 
 %union {
 	std::string *string;
-	struct AstNode *ast;
-	std::map<std::string, AstNode*> *al;
+	struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
+	std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
 	bool boolean;
 }
 
-- 
cgit v1.2.3


From b5a3419ac2c6f367b90f062c4e2252029910cdb9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 4 Aug 2014 15:19:24 +0200
Subject: Added support for non-standard "module mod_name(...);" syntax

---
 frontends/verilog/parser.y | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index c62e761e2..1e0168a5f 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -55,6 +55,7 @@ namespace VERILOG_FRONTEND {
 	struct AstNode *current_ast, *current_ast_mod;
 	int current_function_or_task_port_id;
 	std::vector<char> case_type_stack;
+	bool do_not_require_port_stubs;
 	bool default_nettype_wire;
 	bool sv_mode;
 }
@@ -210,6 +211,7 @@ hierarchical_id:
 
 module:
 	attr TOK_MODULE TOK_ID {
+		do_not_require_port_stubs = false;
 		AstNode *mod = new AstNode(AST_MODULE);
 		current_ast->children.push_back(mod);
 		current_ast_mod = mod;
@@ -244,7 +246,8 @@ single_module_para:
 	};
 
 module_args_opt:
-	'(' ')' | /* empty */ | '(' module_args optional_comma ')';
+	'(' ')' | /* empty */ | '(' module_args optional_comma ')' |
+	'(' '.' '.' '.' ')' { do_not_require_port_stubs = true; };
 
 module_args:
 	module_arg | module_args ',' module_arg;
@@ -582,6 +585,9 @@ wire_name:
 			node->children.push_back($2);
 		}
 		if (current_function_or_task == NULL) {
+			if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
+				port_stubs[*$1] = ++port_counter;
+			}
 			if (port_stubs.count(*$1) != 0) {
 				if (!node->is_input && !node->is_output)
 					frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
-- 
cgit v1.2.3


From 91dd87e60b120119ee34a9961a7b5f33f340282e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Aug 2014 12:15:53 +0200
Subject: Improved scope resolution of local regs in Verilog+AST frontend

---
 frontends/verilog/parser.y | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 1e0168a5f..26e2ddc34 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -599,12 +599,11 @@ wire_name:
 				if (node->is_input || node->is_output)
 					frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
 			}
-			ast_stack.back()->children.push_back(node);
 		} else {
 			if (node->is_input || node->is_output)
 				node->port_id = current_function_or_task_port_id++;
-			current_function_or_task->children.push_back(node);
 		}
+		ast_stack.back()->children.push_back(node);
 		delete $1;
 	};
 
-- 
cgit v1.2.3


From d259abbda2b9d568228dc8d0bed2d0b0d88d7b4f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 6 Aug 2014 15:43:46 +0200
Subject: Added AST_MULTIRANGE (arrays with more than 1 dimension)

---
 frontends/verilog/parser.y | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 26e2ddc34..95d7f3935 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -112,7 +112,8 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_PROPERTY
 
-%type <ast> wire_type range non_opt_range range_or_signed_int expr basic_expr concat_list rvalue lvalue lvalue_concat_list
+%type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
+%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 %type <string> opt_label tok_prim_wrapper hierarchical_id
 %type <boolean> opt_signed
 %type <al> attr
@@ -361,6 +362,15 @@ non_opt_range:
 		$$->children.push_back($2);
 	};
 
+non_opt_multirange:
+	non_opt_range non_opt_range {
+		$$ = new AstNode(AST_MULTIRANGE, $1, $2);
+	} |
+	non_opt_multirange non_opt_range {
+		$$ = $1;
+		$$->children.push_back($2);
+	};
+
 range:
 	non_opt_range {
 		$$ = $1;
@@ -369,6 +379,10 @@ range:
 		$$ = NULL;
 	};
 
+range_or_multirange:
+	range { $$ = $1; } |
+	non_opt_multirange { $$ = $1; };
+
 range_or_signed_int:
 	range {
 		$$ = $1;
@@ -566,7 +580,7 @@ wire_name_and_opt_assign:
 	};
 
 wire_name:
-	TOK_ID range {
+	TOK_ID range_or_multirange {
 		AstNode *node = astbuf1->clone();
 		node->str = *$1;
 		append_attr_clone(node, albuf);
@@ -1007,8 +1021,8 @@ rvalue:
 		$$->str = *$1;
 		delete $1;
 	} |
-	hierarchical_id non_opt_range non_opt_range {
-		$$ = new AstNode(AST_IDENTIFIER, $2, $3);
+	hierarchical_id non_opt_multirange {
+		$$ = new AstNode(AST_IDENTIFIER, $2);
 		$$->str = *$1;
 		delete $1;
 	};
-- 
cgit v1.2.3


From 2dc33337346ea53a654af3d80bdf056c7ccfa43c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Aug 2014 16:41:27 +0200
Subject: Also allow "module foobar(input foo, output bar, ...);" syntax

---
 frontends/verilog/parser.y | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 95d7f3935..f619d3c2b 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -247,8 +247,7 @@ single_module_para:
 	};
 
 module_args_opt:
-	'(' ')' | /* empty */ | '(' module_args optional_comma ')' |
-	'(' '.' '.' '.' ')' { do_not_require_port_stubs = true; };
+	'(' ')' | /* empty */ | '(' module_args optional_comma ')';
 
 module_args:
 	module_arg | module_args ',' module_arg;
@@ -297,7 +296,10 @@ module_arg:
 		ast_stack.back()->children.push_back(node);
 		append_attr(node, $1);
 		delete $4;
-	} module_arg_opt_assignment;
+	} module_arg_opt_assignment |
+	'.' '.' '.' {
+		do_not_require_port_stubs = true;
+	};
 
 wire_type:
 	{
-- 
cgit v1.2.3


From 640d9fc551c546b511f8d64c0ccfc438937164a1 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 18 Aug 2014 14:29:30 +0200
Subject: Added "via_celltype" attribute on task/func

---
 frontends/verilog/parser.y | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index f619d3c2b..bf9b21bb6 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -407,33 +407,35 @@ module_body_stmt:
 	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property;
 
 task_func_decl:
-	TOK_TASK TOK_ID ';' {
+	attr TOK_TASK TOK_ID ';' {
 		current_function_or_task = new AstNode(AST_TASK);
-		current_function_or_task->str = *$2;
+		current_function_or_task->str = *$3;
+		append_attr(current_function_or_task, $1);
 		ast_stack.back()->children.push_back(current_function_or_task);
 		ast_stack.push_back(current_function_or_task);
 		current_function_or_task_port_id = 1;
-		delete $2;
+		delete $3;
 	} task_func_body TOK_ENDTASK {
 		current_function_or_task = NULL;
 		ast_stack.pop_back();
 	} |
-	TOK_FUNCTION opt_signed range_or_signed_int TOK_ID ';' {
+	attr TOK_FUNCTION opt_signed range_or_signed_int TOK_ID ';' {
 		current_function_or_task = new AstNode(AST_FUNCTION);
-		current_function_or_task->str = *$4;
+		current_function_or_task->str = *$5;
+		append_attr(current_function_or_task, $1);
 		ast_stack.back()->children.push_back(current_function_or_task);
 		ast_stack.push_back(current_function_or_task);
 		AstNode *outreg = new AstNode(AST_WIRE);
-		outreg->str = *$4;
-		outreg->is_signed = $2;
-		if ($3 != NULL) {
-			outreg->children.push_back($3);
-			outreg->is_signed = $2 || $3->is_signed;
-			$3->is_signed = false;
+		outreg->str = *$5;
+		outreg->is_signed = $3;
+		if ($4 != NULL) {
+			outreg->children.push_back($4);
+			outreg->is_signed = $3 || $4->is_signed;
+			$4->is_signed = false;
 		}
 		current_function_or_task->children.push_back(outreg);
 		current_function_or_task_port_id = 1;
-		delete $4;
+		delete $5;
 	} task_func_body TOK_ENDFUNCTION {
 		current_function_or_task = NULL;
 		ast_stack.pop_back();
-- 
cgit v1.2.3


From 38addd4c67905e3d1514ba839f07d94058e42560 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Aug 2014 12:42:28 +0200
Subject: Added support for global tasks and functions

---
 frontends/verilog/parser.y | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index bf9b21bb6..acd904e55 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -137,14 +137,21 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 
 %%
 
-input:
-	module input |
-	defattr input |
-	/* empty */ {
-		for (auto &it : default_attr_list)
-			delete it.second;
-		default_attr_list.clear();
-	};
+input: {
+	ast_stack.push_back(current_ast);
+} design {
+	ast_stack.pop_back();
+	log_assert(SIZE(ast_stack) == 0);
+	for (auto &it : default_attr_list)
+		delete it.second;
+	default_attr_list.clear();
+};
+
+design:
+	module design |
+	defattr design |
+	task_func_decl design |
+	/* empty */;
 
 attr:
 	{
@@ -214,9 +221,9 @@ module:
 	attr TOK_MODULE TOK_ID {
 		do_not_require_port_stubs = false;
 		AstNode *mod = new AstNode(AST_MODULE);
-		current_ast->children.push_back(mod);
-		current_ast_mod = mod;
+		ast_stack.back()->children.push_back(mod);
 		ast_stack.push_back(mod);
+		current_ast_mod = mod;
 		port_stubs.clear();
 		port_counter = 0;
 		mod->str = *$3;
@@ -227,7 +234,8 @@ module:
 			frontend_verilog_yyerror("Missing details for module port `%s'.",
 					port_stubs.begin()->first.c_str());
 		ast_stack.pop_back();
-		log_assert(ast_stack.size() == 0);
+		log_assert(ast_stack.size() == 1);
+		current_ast_mod = NULL;
 	};
 
 module_para_opt:
-- 
cgit v1.2.3


From 7bfc4ae12030648cd73686d3779c6d412a3c33c0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Aug 2014 12:43:51 +0200
Subject: Added Verilog/AST support for DPI functions (dpi_call() still
 unimplemented)

---
 frontends/verilog/parser.y | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index acd904e55..1d62bc3be 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -104,7 +104,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
-%token TOK_POSEDGE TOK_NEGEDGE TOK_OR
+%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR
 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
@@ -415,6 +415,16 @@ module_body_stmt:
 	always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property;
 
 task_func_decl:
+	attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
+		current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3));
+		current_function_or_task->str = *$4;
+		append_attr(current_function_or_task, $1);
+		ast_stack.back()->children.push_back(current_function_or_task);
+		delete $3;
+		delete $4;
+	} opt_dpi_function_args ';' {
+		current_function_or_task = NULL;
+	} |
 	attr TOK_TASK TOK_ID ';' {
 		current_function_or_task = new AstNode(AST_TASK);
 		current_function_or_task->str = *$3;
@@ -449,6 +459,27 @@ task_func_decl:
 		ast_stack.pop_back();
 	};
 
+dpi_function_arg:
+	TOK_ID TOK_ID {
+		current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
+		delete $1;
+		delete $2;
+	} |
+	TOK_ID {
+		current_function_or_task->children.push_back(AstNode::mkconst_str(*$1));
+		delete $1;
+	};
+
+opt_dpi_function_args:
+	'(' dpi_function_args ')' |
+	/* empty */;
+
+dpi_function_args:
+	dpi_function_args ',' dpi_function_arg |
+	dpi_function_args ',' |
+	dpi_function_arg |
+	/* empty */;
+
 opt_signed:
 	TOK_SIGNED {
 		$$ = true;
-- 
cgit v1.2.3


From 6c5cafcd8bf4d6b12b4d510480a0ccc1adee7212 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Aug 2014 17:22:04 +0200
Subject: Added support for DPI function with different names in C and Verilog

---
 frontends/verilog/parser.y | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 1d62bc3be..22312c6d1 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -416,7 +416,7 @@ module_body_stmt:
 
 task_func_decl:
 	attr TOK_DPI_FUNCTION TOK_ID TOK_ID {
-		current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3));
+		current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$3), AstNode::mkconst_str(*$4));
 		current_function_or_task->str = *$4;
 		append_attr(current_function_or_task, $1);
 		ast_stack.back()->children.push_back(current_function_or_task);
@@ -425,6 +425,17 @@ task_func_decl:
 	} opt_dpi_function_args ';' {
 		current_function_or_task = NULL;
 	} |
+	attr TOK_DPI_FUNCTION TOK_ID '=' TOK_ID TOK_ID {
+		current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$5), AstNode::mkconst_str(*$3));
+		current_function_or_task->str = *$6;
+		append_attr(current_function_or_task, $1);
+		ast_stack.back()->children.push_back(current_function_or_task);
+		delete $3;
+		delete $5;
+		delete $6;
+	} opt_dpi_function_args ';' {
+		current_function_or_task = NULL;
+	} |
 	attr TOK_TASK TOK_ID ';' {
 		current_function_or_task = new AstNode(AST_TASK);
 		current_function_or_task->str = *$3;
-- 
cgit v1.2.3


From e218f0eacf7cbcfa0736cb2d66bba0010e8e6799 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 22 Aug 2014 14:30:29 +0200
Subject: Added support for non-standard <plugin>:<c_name> DPI syntax

---
 frontends/verilog/parser.y | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 22312c6d1..3512538ca 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -436,6 +436,18 @@ task_func_decl:
 	} opt_dpi_function_args ';' {
 		current_function_or_task = NULL;
 	} |
+	attr TOK_DPI_FUNCTION TOK_ID ':' TOK_ID '=' TOK_ID TOK_ID {
+		current_function_or_task = new AstNode(AST_DPI_FUNCTION, AstNode::mkconst_str(*$7), AstNode::mkconst_str(*$3 + ":" + RTLIL::unescape_id(*$5)));
+		current_function_or_task->str = *$8;
+		append_attr(current_function_or_task, $1);
+		ast_stack.back()->children.push_back(current_function_or_task);
+		delete $3;
+		delete $5;
+		delete $7;
+		delete $8;
+	} opt_dpi_function_args ';' {
+		current_function_or_task = NULL;
+	} |
 	attr TOK_TASK TOK_ID ';' {
 		current_function_or_task = new AstNode(AST_TASK);
 		current_function_or_task->str = *$3;
-- 
cgit v1.2.3


From 19cff41eb4261b20374058f16807a229af46f304 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 23 Aug 2014 15:03:55 +0200
Subject: Changed frontend-api from FILE to std::istream

---
 frontends/verilog/parser.y | 1 +
 1 file changed, 1 insertion(+)

(limited to 'frontends/verilog/parser.y')

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 3512538ca..a9f69a49c 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -58,6 +58,7 @@ namespace VERILOG_FRONTEND {
 	bool do_not_require_port_stubs;
 	bool default_nettype_wire;
 	bool sv_mode;
+	std::istream *lexin;
 }
 YOSYS_NAMESPACE_END
 
-- 
cgit v1.2.3