From b232e027bf18bd37206c15209e23d2f8f7b2a17d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 02:33:12 +0200 Subject: Checking and fixing specify cells in genRTLIL Signed-off-by: Clifford Wolf --- frontends/ast/genrtlil.cc | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'frontends/ast') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index b3a2a84be..b2a22b49a 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1521,9 +1521,23 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } + if (cell->type.in("$specify2", "$specify3")) { + int src_width = GetSize(cell->getPort("\\SRC")); + int dst_width = GetSize(cell->getPort("\\DST")); + bool full = cell->getParam("\\FULL").as_bool(); + if (!full && src_width != dst_width) + log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n"); + if (cell->type == "$specify3") { + int dat_width = GetSize(cell->getPort("\\DAT")); + if (dat_width != dst_width) + log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n"); + } + cell->setParam("\\SRC_WIDTH", Const(src_width)); + cell->setParam("\\DST_WIDTH", Const(dst_width)); + } } break; -- cgit v1.2.3 From 012c6af088a22c035ce1244954b6625188478480 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 22 Apr 2019 09:59:49 +0200 Subject: Allow $specify[23] cells in blackbox modules Signed-off-by: Clifford Wolf --- frontends/ast/ast.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'frontends/ast') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 9f88b08c1..6b3604ee5 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -951,6 +951,9 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast continue; if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM) continue; + if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE && + (child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3")) + continue; blackbox_module = false; break; } @@ -1035,6 +1038,9 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast child->delete_children(); child->children.push_back(AstNode::mkconst_int(0, false, 0)); new_children.push_back(child); + } else if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE && + (child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3")) { + new_children.push_back(child); } else { delete child; } -- cgit v1.2.3 From 71c38d9de527e1a8b55ba295df459fbcf2a0fe47 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 15:46:40 +0200 Subject: Add $specrule cells for $setup/$hold/$skew specify rules Signed-off-by: Clifford Wolf --- frontends/ast/ast.cc | 4 ++-- frontends/ast/genrtlil.cc | 6 ++++++ 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'frontends/ast') diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 6b3604ee5..5623541b2 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -952,7 +952,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM) continue; if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE && - (child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3")) + (child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule")) continue; blackbox_module = false; break; @@ -1039,7 +1039,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast child->children.push_back(AstNode::mkconst_int(0, false, 0)); new_children.push_back(child); } else if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE && - (child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3")) { + (child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule")) { new_children.push_back(child); } else { delete child; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index b2a22b49a..48bd466e6 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1538,6 +1538,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->setParam("\\SRC_WIDTH", Const(src_width)); cell->setParam("\\DST_WIDTH", Const(dst_width)); } + if (cell->type == "$specrule") { + int src_width = GetSize(cell->getPort("\\SRC")); + int dst_width = GetSize(cell->getPort("\\DST")); + cell->setParam("\\SRC_WIDTH", Const(src_width)); + cell->setParam("\\DST_WIDTH", Const(dst_width)); + } } break; -- cgit v1.2.3 From 59d74a334889a17817bbf0c5d3bdef4c59df0c5b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 1 May 2019 09:01:47 +0200 Subject: Re-enable "final loop assignment" feature Signed-off-by: Clifford Wolf --- frontends/ast/simplify.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'frontends/ast') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 4d4b9dfe1..a342bf5d9 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1172,14 +1172,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, varbuf->children[0] = buf; } -#if 0 if (type == AST_FOR) { AstNode *buf = next_ast->clone(); delete buf->children[1]; buf->children[1] = varbuf->children[0]->clone(); current_block->children.insert(current_block->children.begin() + current_block_idx++, buf); } -#endif current_scope[varbuf->str] = backup_scope_varbuf; delete varbuf; -- cgit v1.2.3 From 3b6a02d3a74dc0113d595c6d26a4436160e28a6f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 1 May 2019 09:57:26 +0200 Subject: Fix width detection of memory access with bit slice, fixes #974 Signed-off-by: Clifford Wolf --- frontends/ast/genrtlil.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'frontends/ast') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index b3a2a84be..d4515babf 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -645,6 +645,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (!id_ast->children[0]->range_valid) log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str()); this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1; + if (children.size() > 1) + range = children[1]; } else log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str()); if (range) { -- cgit v1.2.3 From 6bbe2fdbf32e6335cdbecc21547e54992c3a606d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 1 May 2019 10:01:54 +0200 Subject: Add splitcmplxassign test case and silence splitcmplxassign warning Signed-off-by: Clifford Wolf --- frontends/ast/simplify.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/ast') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 4d4b9dfe1..d6561682a 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1607,6 +1607,7 @@ skip_dynamic_range_lvalue_expansion:; current_scope[wire_tmp->str] = wire_tmp; wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false); while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { } + wire_tmp->is_logic = true; AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER); wire_tmp_id->str = wire_tmp->str; -- cgit v1.2.3 From 87426f5a06b0cf9d1fe44efda65e3c048d89d322 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 4 May 2019 08:46:24 +0200 Subject: Improve write_verilog specify support Signed-off-by: Clifford Wolf --- frontends/ast/genrtlil.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'frontends/ast') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 92205b7ae..379fed641 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1492,10 +1492,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) continue; } if (child->type == AST_PARASET) { + int extra_const_flags = 0; IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str; if (child->children[0]->type == AST_REALVALUE) { log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n", log_id(cell), log_id(paraname), child->children[0]->realvalue); + extra_const_flags = RTLIL::CONST_FLAG_REAL; auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue)); strnode->cloneInto(child->children[0]); delete strnode; @@ -1504,6 +1506,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n", log_id(cell), log_id(paraname)); cell->parameters[paraname] = child->children[0]->asParaConst(); + cell->parameters[paraname].flags |= extra_const_flags; continue; } if (child->type == AST_ARGUMENT) { -- cgit v1.2.3