From 00a6c1d9a57da0e0b0fef07b2d618847ed93a9fd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2013 14:31:57 +0200 Subject: Major redesign of expr width/sign detecion (verilog/ast frontend) --- frontends/ast/ast.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'frontends/ast/ast.h') diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 12e9a71bc..99760e09c 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -174,10 +174,14 @@ namespace AST void dumpAst(FILE *f, std::string indent, AstNode *other = NULL); void dumpVlog(FILE *f, std::string indent); + // used by genRTLIL() for detecting expression width and sign + void detectSignWidthWorker(int &width_hint, bool &sign_hint); + void detectSignWidth(int &width_hint, bool &sign_hint); + // create RTLIL code for this AST node // for expressions the resulting signal vector is returned // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module - RTLIL::SigSpec genRTLIL(int width_hint = -1); + RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false); RTLIL::SigSpec genWidthRTLIL(int width, RTLIL::SigSpec *subst_from = NULL, RTLIL::SigSpec *subst_to = NULL); // compare AST nodes -- cgit v1.2.3