From 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 23:41:18 -0700
Subject: Consistent use of 'override' for virtual methods in derived classes.

o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
---
 examples/cxx-api/evaldemo.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'examples')

diff --git a/examples/cxx-api/evaldemo.cc b/examples/cxx-api/evaldemo.cc
index e5cc8d8e7..34373487d 100644
--- a/examples/cxx-api/evaldemo.cc
+++ b/examples/cxx-api/evaldemo.cc
@@ -22,7 +22,7 @@ struct EvalDemoPass : public Pass
 {
 	EvalDemoPass() : Pass("evaldemo") { }
 
-	virtual void execute(vector<string>, Design *design)
+	void execute(vector<string>, Design *design) YS_OVERRIDE
 	{
 		Module *module = design->top_module();
 
-- 
cgit v1.2.3


From beedaa58561eb7cabf24e0d267beb77d5c78ef1d Mon Sep 17 00:00:00 2001
From: japm48 <japm48@users.noreply.github.com>
Date: Sun, 22 Jul 2018 22:29:31 +0200
Subject: fix basys3 example

Added `CONFIG_VOLTAGE` and `CFGBVS` to constraints file
to avoid warning `DRC 23-20`.

Added `open_hw` needed for programming.
---
 examples/basys3/example.xdc  | 3 +++
 examples/basys3/run_prog.tcl | 1 +
 2 files changed, 4 insertions(+)

(limited to 'examples')

diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc
index c1fd0e925..8cdaa1996 100644
--- a/examples/basys3/example.xdc
+++ b/examples/basys3/example.xdc
@@ -19,3 +19,6 @@ set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1  } [get_ports {LD[15]}]
 
 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
 
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
diff --git a/examples/basys3/run_prog.tcl b/examples/basys3/run_prog.tcl
index d711af840..b078ad511 100644
--- a/examples/basys3/run_prog.tcl
+++ b/examples/basys3/run_prog.tcl
@@ -1,3 +1,4 @@
+open_hw
 connect_hw_server
 open_hw_target [lindex [get_hw_targets] 0]
 set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0]
-- 
cgit v1.2.3


From c151bb31eb9bc905f3a91803a2f4ea882a254b3c Mon Sep 17 00:00:00 2001
From: Benedikt Tutzer <e1225461@student.tuwien.ac.at>
Date: Tue, 11 Dec 2018 08:13:42 +0100
Subject: Added sample code for python-api

---
 examples/python-api/.gitignore       |   1 +
 examples/python-api/netlist_graph.py | 472 +++++++++++++++++++++++++++++++++++
 examples/python-api/run.sh           |   6 +
 3 files changed, 479 insertions(+)
 create mode 100644 examples/python-api/.gitignore
 create mode 100644 examples/python-api/netlist_graph.py
 create mode 100755 examples/python-api/run.sh

(limited to 'examples')

diff --git a/examples/python-api/.gitignore b/examples/python-api/.gitignore
new file mode 100644
index 000000000..758de1134
--- /dev/null
+++ b/examples/python-api/.gitignore
@@ -0,0 +1 @@
+out/**
diff --git a/examples/python-api/netlist_graph.py b/examples/python-api/netlist_graph.py
new file mode 100644
index 000000000..c8da76e3d
--- /dev/null
+++ b/examples/python-api/netlist_graph.py
@@ -0,0 +1,472 @@
+from libyosys import *
+from scipy.sparse import coo_matrix
+from numpy import savetxt
+
+from enum import Enum
+class NodeType(Enum):
+	GRAPH_CELL = 0
+	GRAPH_PI = 1
+	GRAPH_PO = 2
+	GRAPH_CONST = 3
+	GRAPH_WIRE = 4
+
+class NetlistElement:
+
+	def __init__(self, design, module, name):
+		self.design = design
+		self.module = module
+		self.name = name
+
+class Bit(NetlistElement):
+
+	def __init__(self, bit, design, module, node, port, pos):
+		super().__init__(design, module, IdString("\\__BIT__"))
+		self.bit = bit
+		self.node = node
+		self.port = port
+		self.pos = pos
+
+class Port(NetlistElement):
+
+	def __init__(self, name):
+		super().__init__(None, None, name)
+		self.input = False
+		self.output = False
+		self.bits = []
+
+class Node(NetlistElement):
+
+	def __init__(self, design, module, name, nodeType):
+		super().__init__(design, module, name)
+		self.nodeType = nodeType
+		self.ports = []
+
+	def __lt__(self, other):
+		if isinstance(other, self.__class):
+			if self.type == other.type:
+				return self.name.str() < other.name.str()
+			return self.type < other.type
+		return False
+
+class PyCell(Node):
+
+	def __init__(self, design, module, name, cell):
+		super().__init__(design, module, name, NodeType.GRAPH_CELL)
+		self.cell = cell
+
+class PyWire(Node):
+
+	def __init__(self, design, module, name):
+		super().__init__(design, module, name, NodeType.GRAPH_WIRE)
+
+class NetlistGraph:
+
+	def __init__(self, design, module = None):
+		self.design = design
+		if module != None:
+			self.module = module
+		else:
+			self.module = list(design.modules_.values())[0]
+		self.cells = []
+		self.wires = []
+		self.nodes = []
+		self.node_bits = []
+		self.wire_bits = []
+		self.node_index = {}
+		self.node_bit_index = {}
+		self.wire_bit_index = {}
+
+		self.incoming = None
+		self.outgoing = None
+		self.create()
+
+	def create(self):
+
+		log_header(self.design, "Creating abstract graph representation of "
+				+ "module " + self.module.name.str() + "\n")
+		log_push()
+
+		sigmap = SigMap(self.module)
+		
+		log("  Creating const node\n")
+		const_node = Node(self.design, self.module, IdString("\\__CONST__"), NodeType.GRAPH_CONST)
+		const_port = Port(IdString("\\__CONST__"))
+		const_port.input = False
+		const_port.output = True
+		cb = SigBit(State.Sx)
+		const_bit = Bit(cb, self.design, self.module, const_node, const_port, 0)
+		const_node.ports.append(const_port)
+		const_port.bits.append(const_bit)
+
+		self.nodes.append(const_node)
+		self.wires.append(const_node)
+		log("  Creating cell nodes\n")
+
+		for cell in self.module.selected_cells():
+			c = PyCell(self.design, self.module, cell.name, cell)
+			for first, second in cell.connections_.items():
+				p = Port(first)
+				p.input = cell.input(p.name)
+				p.output = cell.output(p.name)
+				for bit in sigmap(second).to_sigbit_vector():
+					b = Bit(bit, self.design, self.module, c, p, len(p.bits))
+					p.bits.append(b)
+				c.ports.append(p)
+
+			self.cells.append(c)
+
+		log("  Creating wire nodes\n")
+
+		for wire in self.module.selected_wires():
+			node = PyWire(self.design, self.module, wire.name)
+			p = Port(IdString(""))
+			if wire.port_input:
+				node.nodeType = NodeType.GRAPH_PI
+				p.name = IdString("\\PI")
+				p.input = False
+				p.output = True
+			elif wire.port_output:
+				node.nodeType = NodeType.GRAPH_PO
+				p.name = IdString("\\PO")
+				p.input = True
+				p.output = False
+			for bit in sigmap(wire).to_sigbit_set():
+				b = Bit(bit, self.design, self.module, node, p, len(p.bits))
+				p.bits.append(b)
+			node.ports.append(p)
+			self.wires.append(node)
+
+		self.nodes.extend(self.cells)
+		self.nodes.extend(wire for wire in self.wires if wire.nodeType in [NodeType.GRAPH_PI, NodeType.GRAPH_PO])
+
+		log("  Creating node index for fast lookup\n")
+
+		idx = 0
+
+		for node in self.nodes:
+			self.node_index[node.name] = idx
+			idx += 1
+
+		log("  Creating node bits (= const + cell + PI + PO)\n")
+
+		for node in self.nodes:
+			for port in node.ports:
+				for bit in port.bits:
+					self.node_bits.append(bit)
+
+		log("  Creating wire bits\n")
+
+		for wire in self.wires:
+			for port in wire.ports:
+				for bit in port.bits:
+					self.wire_bits.append(bit)
+
+		log("  Creating node bit index for fast lookup\n")
+
+		idx = 0
+
+		for bit in self.node_bits:
+			self.node_bit_index[bit] = idx
+			idx += 1
+
+		log("  Creating wire bit index for fast lookup\n")
+
+		idx = 0
+
+		for bit in self.wire_bits:
+			self.wire_bit_index[bit] = idx
+			idx += 1
+
+		log("  Mapping port.wire connections to wire bit index\n")
+
+		idx = 0
+
+		wbitmap = {}
+		for wbit in self.wire_bits:
+			wbitmap[wbit.bit] = idx
+			idx += 1
+
+		inputTriplets = []
+		outputTriplets = [(0,0,1)]
+
+		log("  Mapping node bits to wire bits\n")
+
+		idx = 0
+
+		for nbit in self.node_bits:
+			row = idx
+			idx += 1
+			col = 0
+			val = 1
+
+			def check_wire():
+				nonlocal nbit
+				try:
+					wire = nbit.bit.wire
+					return True
+				except:
+					return False
+
+			if check_wire() and not self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
+				continue
+
+			if check_wire():
+				col = wbitmap[nbit.bit]
+
+			triplet = (row, col, val)
+
+			if col == 0 and row != 0:
+				inputTriplets.append(triplet)
+				continue
+
+			if nbit.node.nodeType == NodeType.GRAPH_CELL:
+				cell = nbit.node
+				if check_wire() and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
+					if cell.cell.input(nbit.port.name):
+						inputTriplets.append(triplet)
+					if cell.cell.output(nbit.port.name):
+						outputTriplets.append(triplet)
+				continue
+
+			if nbit.node.nodeType == NodeType.GRAPH_PI and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
+				outputTriplets.append(triplet)
+				continue
+
+			if nbit.node.nodeType == NodeType.GRAPH_PO and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
+				inputTriplets.append(triplet)
+				continue
+
+		log("  Creating port-to-wire incidence matrices\n")
+
+		sizeX = len(self.node_bits)
+		sizeY= len(self.wire_bits)
+
+		inputRows = [i[0] for i in inputTriplets]
+		inputCols = [i[1] for i in inputTriplets]
+		inputVals = [i[2] for i in inputTriplets]
+		self.incoming = coo_matrix((inputVals, (inputRows, inputCols)), shape=(sizeX, sizeY), dtype='int32')
+
+		outputRows = [i[0] for i in outputTriplets]
+		outputCols = [i[1] for i in outputTriplets]
+		outputVals = [i[2] for i in outputTriplets]
+		self.outgoing = coo_matrix((outputVals, (outputRows, outputCols)), shape=(sizeX, sizeY), dtype='int32')
+
+	def dot(self):
+		log_header(self.design, "Creating 'dot' bipartite module graph representation of module " + self.module.name.str() + "\n")
+		log_push()
+		bitmap = {}
+
+		ss  = "digraph g{\n"
+		ss += "  rankdir = LR\n"
+		nidx = 0
+		pidx = 0
+		bidx = 0
+		cells_wires = []
+		cells_wires.extend(self.cells)
+		cells_wires.extend(self.wires)
+
+		idx = 0
+
+		for node in cells_wires:
+			for port in node.ports:
+				for bit in port.bits:
+					bitmap[bit] = idx
+					idx += 1
+		
+		for node in cells_wires:
+			ss += "  subgraph cluster" + str(nidx) + " {\n"
+			ss += "    style = \"setlinewidth(2)\";\n"
+			ss += "    margin = .2;\n"
+			ss += "    n" + str(node.name.index_)
+
+			def s_cell():
+				nonlocal ss
+				ss += "[shape=ellipse,label=\"" + str(nidx) + ":"
+				ss += unescape_id(node.cell.type) + "\""
+			def s_pi():
+				nonlocal ss
+				ss += "[shape = box, label=\"" + str(nidx) + ":"
+				ss += unescape_id(node.name.str()) + "\""
+			def s_po():
+				nonlocal ss
+				ss += "[shape = diamond, label=\"" + str(nidx) + ":"
+				ss += unescape_id(node.name.str()) + "\""
+			def s_const():
+				nonlocal ss
+				ss += "[shape = octagon, label=\"" + str(nidx) + ":CO\""
+			def s_wire():
+				nonlocal ss
+				ss += "[shape = plaintext, label=\"" + str(nidx - len(self.cells)) + ":"
+				ss += unescape_id(node.name.str()) + "\""
+			switch = {
+					NodeType.GRAPH_CELL : s_cell,
+					NodeType.GRAPH_PI : s_pi,
+					NodeType.GRAPH_PO : s_po,
+					NodeType.GRAPH_CONST : s_const,
+					NodeType.GRAPH_WIRE : s_wire
+					}
+			switch[node.nodeType]()
+
+			ss += "];\n"
+
+			pidx = 0
+			for port in node.ports:
+				ss += "    port_" + str(node.name.index_) + "_" + str(port.name.index_)
+				ss += "[shape=none,label=<\n"
+				ss += "      <table border=\"0\" cellborder=\"1\" cellspacing=\"0\" cellpadding=\"4\" >\n"
+				ss += "        <tr><td bgcolor=\"lightgray\" port=\"p" + str(node.name.index_) + "_"
+				ss += str(port.name.index_) + "\"> "
+				ss += unescape_id(port.name.str())
+				ss += "</td></tr>\n"
+	
+				bidx = 0;
+				for bit in port.bits:
+
+					ss += "          <tr><td bgcolor=\"white\" port=\"b" + str(node.name.index_) + "_" + str(port.name.index_) + "_" + str(bit.pos) + "\"> " + str(bitmap[bit]) + ":"  + str(bidx) + "</td></tr>\n"
+
+					bidx += 1
+
+				ss += "      </table>\n    >];\n"
+
+				if node.nodeType == NodeType.GRAPH_CELL:
+					if node.cell.output(port.name):
+						ss += "    n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n"
+					else:
+						ss += "    port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) +  ";\n"
+				if node.nodeType == NodeType.GRAPH_PI or node.nodeType == NodeType.GRAPH_CONST:
+					ss += "    n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n"
+				if node.nodeType == NodeType.GRAPH_PO:
+					ss += "    port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) +  ";\n"
+
+				pidx += 1
+			ss += "  }\n"
+			nidx += 1
+
+		for i in range(len(self.incoming.nonzero()[0])):
+			b1 = self.node_bits[self.incoming.nonzero()[0][i]]
+			b2 = self.wire_bits[self.incoming.nonzero()[1][i]]
+
+			if b1.node.nodeType == NodeType.GRAPH_PO or b1.node.nodeType == NodeType.GRAPH_CONST:
+				continue
+
+			ss += "  "
+			ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":"
+			ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos)
+			ss += " -> "
+			ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":"
+			ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos)
+			ss += ";\n"
+
+		for i in range(len(self.outgoing.nonzero()[0])):
+			b1 = self.node_bits[self.outgoing.nonzero()[0][i]]
+			b2 = self.wire_bits[self.outgoing.nonzero()[1][i]]
+
+			if b1.node.nodeType == NodeType.GRAPH_PI:
+				continue
+
+			ss += "  "
+			ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":"
+			ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos)
+			ss += " -> "
+			ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":"
+			ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos)
+			ss += ";\n"
+
+		ss += "}\n"
+
+		log_pop()
+
+		return ss
+
+	def save_dot(self, filename):
+		savetxt(filename, [self.dot()], fmt="%s")
+
+	def save_incoming(self, filename, delimiter = ","):
+		savetxt(filename, self.incoming.todense(), "%d", delimiter=delimiter)
+
+	def save_outgoing(self, filename, delimiter = ","):
+		savetxt(filename, self.outgoing.todense(), "%d", delimiter=delimiter)
+
+	def save_adjacency(self, filename, delimiter = ","):
+		savetxt(filename, (self.outgoing*self.incoming.transpose()).todense(), "%d", delimiter=delimiter)
+
+p = None
+
+class NetlistGraphPass(Pass):
+
+	def __init__(self):
+		super().__init__("netlist_graph", "Generates the Netlist-Graph of a module")
+
+		import argparse
+		self.parser = argparse.ArgumentParser()
+
+		self.parser.add_argument("-mod", nargs=1, metavar="MOD", help="The Netlist-Graph of the module with the id-string <module> will be generated. If this argument is not given, the first module will be used")
+		self.parser.add_argument("-dot", nargs=1, metavar="FILE", help="Write the Netlist-Graph to FILE in dot format")
+		self.parser.add_argument("-i","-incoming", nargs=1, metavar="FILE", help="Write the incoming incidence matrix to FILE in csv format")
+		self.parser.add_argument("-o","-outgoing", nargs=1, metavar="FILE", help="Write the outgoing incidence matrix to FILE in csv format")
+		self.parser.add_argument("-a","-adjacency", nargs=1, metavar="FILE", help="Write the adjacency matrix to FILE in csv format")
+
+	def py_help(self):
+
+		log("This pass generates the Netlist-Graph of a module\n")
+		log(self.parser.format_help())
+
+	def py_execute(self, args, des):
+
+		args = self.parser.parse_args(args[1:])
+
+		graph = None
+		if args.mod:
+			try:
+				graph = NetlistGraph(des, des.modules_[IdString(args.mod[0])])
+			except KeyError:
+				log("Module \"" + args.mod[0] + "\" not found!\n")
+				exit()
+		else:
+			graph = NetlistGraph(des, list(des.modules_.values())[0])
+
+		if args.dot:
+			graph.save_dot(args.dot[0])
+
+		if args.i:
+			graph.save_incoming(args.i[0])
+
+		if args.o:
+			graph.save_outgoing(args.o[0])
+
+		if args.a:
+			graph.save_adjacency(args.a[0])
+	
+	def py_clear_flags(self):
+		log("Clear\n")
+
+if __name__ == "__main__":
+
+	designs = {}
+	graphs = {}
+
+	testdir = "../../tests/simple/"
+
+	import os
+	for testcase in os.listdir(testdir):
+		if not testcase.endswith(".v"):
+			continue
+		designs[testcase] = Design()
+		run_pass("read_verilog " + testdir + testcase, designs[testcase])
+		run_pass("hierarchy -check -auto-top", designs[testcase])
+		run_pass("proc", designs[testcase])
+		run_pass("clean", designs[testcase])
+		run_pass("memory", designs[testcase])
+		run_pass("clean", designs[testcase])
+		run_pass("opt -full", designs[testcase])
+		run_pass("clean", designs[testcase])
+		graphs[testcase] = NetlistGraph(designs[testcase])
+
+		file_prefix = "out/" + testcase
+		graphs[testcase].save_dot(file_prefix + ".dot")
+		graphs[testcase].save_incoming(file_prefix + "_in.csv")
+		graphs[testcase].save_outgoing(file_prefix + "_out.csv")
+		graphs[testcase].save_adjacency(file_prefix + "_adjacency.csv")
+
+else:
+	p = NetlistGraphPass()
diff --git a/examples/python-api/run.sh b/examples/python-api/run.sh
new file mode 100755
index 000000000..5852ea9ac
--- /dev/null
+++ b/examples/python-api/run.sh
@@ -0,0 +1,6 @@
+PYTHONPATH=`pwd`/../../:$PYTHONPATH
+mkdir -p out
+if [ ! -f ../../libyosys.so ]; then
+	make -C ../..
+fi
+python3.5 netlist_graph.py
-- 
cgit v1.2.3


From f589ce86bac3169281a077248af328f6758ff0eb Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 5 Jan 2019 17:02:01 +0100
Subject: Add skeleton Yosys-Libero igloo2 example project

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/.gitignore |  2 ++
 examples/igloo2/example.v  | 22 ++++++++++++++++++++++
 examples/igloo2/example.ys |  2 ++
 examples/igloo2/libero.sh  |  4 ++++
 examples/igloo2/libero.tcl | 14 ++++++++++++++
 5 files changed, 44 insertions(+)
 create mode 100644 examples/igloo2/.gitignore
 create mode 100644 examples/igloo2/example.v
 create mode 100644 examples/igloo2/example.ys
 create mode 100644 examples/igloo2/libero.sh
 create mode 100644 examples/igloo2/libero.tcl

(limited to 'examples')

diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore
new file mode 100644
index 000000000..ae86e69cc
--- /dev/null
+++ b/examples/igloo2/.gitignore
@@ -0,0 +1,2 @@
+/example.edn
+/work
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
new file mode 100644
index 000000000..3eb7007c5
--- /dev/null
+++ b/examples/igloo2/example.v
@@ -0,0 +1,22 @@
+module top (
+	input  clk,
+	output LED1,
+	output LED2,
+	output LED3,
+	output LED4,
+	output LED5
+);
+
+	localparam BITS = 5;
+	localparam LOG2DELAY = 22;
+
+	reg [BITS+LOG2DELAY-1:0] counter = 0;
+	reg [BITS-1:0] outcnt;
+
+	always @(posedge clk) begin
+		counter <= counter + 1;
+		outcnt <= counter >> LOG2DELAY;
+	end
+
+	assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
+endmodule
diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys
new file mode 100644
index 000000000..75a305d86
--- /dev/null
+++ b/examples/igloo2/example.ys
@@ -0,0 +1,2 @@
+read_verilog example.v
+synth_sf2 -top top -edif example.edn
diff --git a/examples/igloo2/libero.sh b/examples/igloo2/libero.sh
new file mode 100644
index 000000000..582f6ccb9
--- /dev/null
+++ b/examples/igloo2/libero.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+set -ex
+rm -rf work
+LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
new file mode 100644
index 000000000..cc1ab2403
--- /dev/null
+++ b/examples/igloo2/libero.tcl
@@ -0,0 +1,14 @@
+# Run with "libero SCRIPT:libero.tcl"
+
+new_project \
+    -name top \
+    -location work \
+    -family IGLOO2 \
+    -die PA4MGL500 \
+    -package tq144 \
+    -speed -1 \
+    -hdl VERILOG
+
+import_files -edif {example.edn}
+run_tool –name {COMPILE}
+run_tool –name {PLACEROUTEN}
-- 
cgit v1.2.3


From 2a2e0a4722ded7628b71f436b94a06aebd57bb62 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 8 Jan 2019 20:16:36 +0100
Subject: Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/.gitignore |  3 ++-
 examples/igloo2/example.ys |  3 ++-
 examples/igloo2/libero.sh  |  4 ----
 examples/igloo2/libero.tcl | 27 ++++++++++++++++++++++++---
 examples/igloo2/runme.sh   |  5 +++++
 5 files changed, 33 insertions(+), 9 deletions(-)
 delete mode 100644 examples/igloo2/libero.sh
 create mode 100644 examples/igloo2/runme.sh

(limited to 'examples')

diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore
index ae86e69cc..fa3c3d7ed 100644
--- a/examples/igloo2/.gitignore
+++ b/examples/igloo2/.gitignore
@@ -1,2 +1,3 @@
-/example.edn
+/netlist.edn
+/netlist.v
 /work
diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys
index 75a305d86..872f97b99 100644
--- a/examples/igloo2/example.ys
+++ b/examples/igloo2/example.ys
@@ -1,2 +1,3 @@
 read_verilog example.v
-synth_sf2 -top top -edif example.edn
+synth_sf2 -top top -edif netlist.edn
+write_verilog netlist.v
diff --git a/examples/igloo2/libero.sh b/examples/igloo2/libero.sh
deleted file mode 100644
index 582f6ccb9..000000000
--- a/examples/igloo2/libero.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/bash
-set -ex
-rm -rf work
-LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index cc1ab2403..9f6d3b792 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -9,6 +9,27 @@ new_project \
     -speed -1 \
     -hdl VERILOG
 
-import_files -edif {example.edn}
-run_tool –name {COMPILE}
-run_tool –name {PLACEROUTEN}
+# import_files -edif "[pwd]/netlist.edn"
+
+import_files -hdl_source "[pwd]/netlist.v"
+set_root top
+
+save_project
+
+puts "**> SYNTHESIZE"
+run_tool -name {SYNTHESIZE}
+puts "<** SYNTHESIZE"
+
+puts "**> COMPILE"
+run_tool -name {COMPILE}
+puts "<** COMPILE"
+
+puts "**> PLACEROUTE"
+run_tool -name {PLACEROUTE}
+puts "<** PLACEROUTE"
+
+# puts "**> export_bitstream"
+# export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
+# puts "<** export_bitstream"
+
+exit 0
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
new file mode 100644
index 000000000..4edfb5409
--- /dev/null
+++ b/examples/igloo2/runme.sh
@@ -0,0 +1,5 @@
+#!/bin/bash
+set -ex
+rm -rf work
+yosys example.ys
+LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl
-- 
cgit v1.2.3


From 9b277fc21ea455a0e0ca9b7acde039e90ddb380d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Jan 2019 13:35:52 +0100
Subject: Improve Igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/.gitignore     |  4 ++--
 examples/igloo2/example.fp.pdc |  0
 examples/igloo2/example.io.pdc |  0
 examples/igloo2/example.sdc    |  0
 examples/igloo2/example.v      |  2 +-
 examples/igloo2/example.ys     |  4 ++--
 examples/igloo2/libero.tcl     | 50 +++++++++++++++++++++++++++++-------------
 examples/igloo2/runme.sh       |  3 +--
 8 files changed, 41 insertions(+), 22 deletions(-)
 create mode 100644 examples/igloo2/example.fp.pdc
 create mode 100644 examples/igloo2/example.io.pdc
 create mode 100644 examples/igloo2/example.sdc

(limited to 'examples')

diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore
index fa3c3d7ed..ea58efc9f 100644
--- a/examples/igloo2/.gitignore
+++ b/examples/igloo2/.gitignore
@@ -1,3 +1,3 @@
 /netlist.edn
-/netlist.v
-/work
+/netlist.vm
+/proj
diff --git a/examples/igloo2/example.fp.pdc b/examples/igloo2/example.fp.pdc
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/igloo2/example.io.pdc b/examples/igloo2/example.io.pdc
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 3eb7007c5..0e336e557 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -1,4 +1,4 @@
-module top (
+module example (
 	input  clk,
 	output LED1,
 	output LED2,
diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys
index 872f97b99..04ea02672 100644
--- a/examples/igloo2/example.ys
+++ b/examples/igloo2/example.ys
@@ -1,3 +1,3 @@
 read_verilog example.v
-synth_sf2 -top top -edif netlist.edn
-write_verilog netlist.v
+synth_sf2 -top example -edif netlist.edn
+write_verilog netlist.vm
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 9f6d3b792..b2090f402 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -1,24 +1,38 @@
 # Run with "libero SCRIPT:libero.tcl"
 
+file delete -force proj
+
 new_project \
-    -name top \
-    -location work \
+    -name example \
+    -location proj \
+    -block_mode 1 \
+    -hdl "VERILOG" \
     -family IGLOO2 \
     -die PA4MGL500 \
     -package tq144 \
-    -speed -1 \
-    -hdl VERILOG
-
-# import_files -edif "[pwd]/netlist.edn"
-
-import_files -hdl_source "[pwd]/netlist.v"
-set_root top
-
-save_project
-
-puts "**> SYNTHESIZE"
-run_tool -name {SYNTHESIZE}
-puts "<** SYNTHESIZE"
+    -speed -1
+
+import_files -hdl_source {netlist.vm}
+import_files -sdc {example.sdc}
+import_files -io_pdc {example.io.pdc}
+import_files -fp_pdc {example.fp.pdc}
+set_option -synth 0
+
+organize_tool_files -tool PLACEROUTE \
+    -file {proj/constraint/example.sdc} \
+    -file {proj/constraint/io/example.io.pdc} \
+    -file {proj/constraint/fp/example.fp.pdc} \
+    -input_type constraint
+
+organize_tool_files -tool VERIFYTIMING \
+    -file {proj/constraint/example.sdc} \
+    -input_type constraint
+
+configure_tool -name PLACEROUTE \
+    -params TDPR:true \
+    -params PDPR:false \
+    -params EFFORT_LEVEL:false \
+    -params REPAIR_MIN_DELAY:false
 
 puts "**> COMPILE"
 run_tool -name {COMPILE}
@@ -28,6 +42,12 @@ puts "**> PLACEROUTE"
 run_tool -name {PLACEROUTE}
 puts "<** PLACEROUTE"
 
+puts "**> VERIFYTIMING"
+run_tool -name {VERIFYTIMING}
+puts "<** VERIFYTIMING"
+
+save_project
+
 # puts "**> export_bitstream"
 # export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
 # puts "<** export_bitstream"
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index 4edfb5409..54247759f 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,5 +1,4 @@
 #!/bin/bash
 set -ex
-rm -rf work
-yosys example.ys
+yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
 LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl
-- 
cgit v1.2.3


From db5765b443c26b5b2dc3ac56d5a448fc8b861d43 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Jan 2019 14:38:37 +0100
Subject: Add SF2 IO buffer insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.v  | 3 ++-
 examples/igloo2/libero.tcl | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

(limited to 'examples')

diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 0e336e557..1a1967d5a 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -1,5 +1,6 @@
 module example (
 	input  clk,
+	input  EN,
 	output LED1,
 	output LED2,
 	output LED3,
@@ -14,7 +15,7 @@ module example (
 	reg [BITS-1:0] outcnt;
 
 	always @(posedge clk) begin
-		counter <= counter + 1;
+		counter <= counter + EN;
 		outcnt <= counter >> LOG2DELAY;
 	end
 
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index b2090f402..952342a4c 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -5,7 +5,7 @@ file delete -force proj
 new_project \
     -name example \
     -location proj \
-    -block_mode 1 \
+    -block_mode 0 \
     -hdl "VERILOG" \
     -family IGLOO2 \
     -die PA4MGL500 \
-- 
cgit v1.2.3


From f3556e9f7ac6947be440a51699af773655de4911 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Jan 2019 14:54:04 +0100
Subject: Cleanups in igloo2 example design

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.fp.pdc | 0
 examples/igloo2/example.io.pdc | 0
 examples/igloo2/example.pdc    | 1 +
 examples/igloo2/example.sdc    | 1 +
 examples/igloo2/example.ys     | 3 ---
 examples/igloo2/libero.tcl     | 6 ++----
 6 files changed, 4 insertions(+), 7 deletions(-)
 delete mode 100644 examples/igloo2/example.fp.pdc
 delete mode 100644 examples/igloo2/example.io.pdc
 create mode 100644 examples/igloo2/example.pdc
 delete mode 100644 examples/igloo2/example.ys

(limited to 'examples')

diff --git a/examples/igloo2/example.fp.pdc b/examples/igloo2/example.fp.pdc
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/igloo2/example.io.pdc b/examples/igloo2/example.io.pdc
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc
new file mode 100644
index 000000000..e6ffd53db
--- /dev/null
+++ b/examples/igloo2/example.pdc
@@ -0,0 +1 @@
+# Add placement constraints here
diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
index e69de29bb..c6ff94161 100644
--- a/examples/igloo2/example.sdc
+++ b/examples/igloo2/example.sdc
@@ -0,0 +1 @@
+# Add timing constraints here
diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys
deleted file mode 100644
index 04ea02672..000000000
--- a/examples/igloo2/example.ys
+++ /dev/null
@@ -1,3 +0,0 @@
-read_verilog example.v
-synth_sf2 -top example -edif netlist.edn
-write_verilog netlist.vm
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 952342a4c..1f3476316 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -14,14 +14,12 @@ new_project \
 
 import_files -hdl_source {netlist.vm}
 import_files -sdc {example.sdc}
-import_files -io_pdc {example.io.pdc}
-import_files -fp_pdc {example.fp.pdc}
+import_files -io_pdc {example.pdc}
 set_option -synth 0
 
 organize_tool_files -tool PLACEROUTE \
     -file {proj/constraint/example.sdc} \
-    -file {proj/constraint/io/example.io.pdc} \
-    -file {proj/constraint/fp/example.fp.pdc} \
+    -file {proj/constraint/io/example.pdc} \
     -input_type constraint
 
 organize_tool_files -tool VERIFYTIMING \
-- 
cgit v1.2.3


From a176ac95ded8b5aa9efb98b7a8e6981c90827d0e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 3 Mar 2019 21:35:57 -0800
Subject: Update igloo2 example to Libero v12.0

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/libero.tcl | 9 ++++-----
 examples/igloo2/runme.sh   | 2 +-
 2 files changed, 5 insertions(+), 6 deletions(-)

(limited to 'examples')

diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 1f3476316..82e614cd4 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -15,6 +15,7 @@ new_project \
 import_files -hdl_source {netlist.vm}
 import_files -sdc {example.sdc}
 import_files -io_pdc {example.pdc}
+build_design_hierarchy
 set_option -synth 0
 
 organize_tool_files -tool PLACEROUTE \
@@ -44,10 +45,8 @@ puts "**> VERIFYTIMING"
 run_tool -name {VERIFYTIMING}
 puts "<** VERIFYTIMING"
 
-save_project
-
-# puts "**> export_bitstream"
-# export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
-# puts "<** export_bitstream"
+puts "**> export_bitstream"
+export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
+puts "<** export_bitstream"
 
 exit 0
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index 54247759f..95f2282ba 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,4 +1,4 @@
 #!/bin/bash
 set -ex
 yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
-LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl
+LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
-- 
cgit v1.2.3


From 107d8848041289bdf3ed85f2ca6c7e02fa9ec774 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 3 Mar 2019 23:54:35 -0800
Subject: Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/libero.tcl | 9 +++++++--
 examples/igloo2/runme.sh   | 4 +++-
 2 files changed, 10 insertions(+), 3 deletions(-)

(limited to 'examples')

diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 82e614cd4..6f7d4e24b 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -33,20 +33,25 @@ configure_tool -name PLACEROUTE \
     -params EFFORT_LEVEL:false \
     -params REPAIR_MIN_DELAY:false
 
+puts ""
 puts "**> COMPILE"
 run_tool -name {COMPILE}
 puts "<** COMPILE"
 
+puts ""
 puts "**> PLACEROUTE"
 run_tool -name {PLACEROUTE}
 puts "<** PLACEROUTE"
 
+puts ""
 puts "**> VERIFYTIMING"
 run_tool -name {VERIFYTIMING}
 puts "<** VERIFYTIMING"
 
-puts "**> export_bitstream"
+puts ""
+puts "**> BITSTREAM"
 export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
-puts "<** export_bitstream"
+puts "<** BITSTREAM"
 
+puts ""
 exit 0
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index 95f2282ba..a08894e0a 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,4 +1,6 @@
 #!/bin/bash
 set -ex
 yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
-LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
+export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
+/opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
+cp proj/designer/example/export/example.stp .
-- 
cgit v1.2.3


From 32a901ddf21711e2b2fe2a0a8719ff7f69fd9489 Mon Sep 17 00:00:00 2001
From: Kali Prasad <kprasadvnsi@pm.me>
Date: Mon, 4 Mar 2019 23:26:56 +0530
Subject: Added examples/anlogic/

---
 examples/anlogic/.gitignore |  4 ++++
 examples/anlogic/README     | 13 +++++++++++++
 examples/anlogic/build.sh   |  4 ++++
 examples/anlogic/build.tcl  | 11 +++++++++++
 examples/anlogic/demo.adc   |  2 ++
 examples/anlogic/demo.v     | 18 ++++++++++++++++++
 examples/anlogic/demo.ys    |  3 +++
 7 files changed, 55 insertions(+)
 create mode 100644 examples/anlogic/.gitignore
 create mode 100644 examples/anlogic/README
 create mode 100755 examples/anlogic/build.sh
 create mode 100644 examples/anlogic/build.tcl
 create mode 100644 examples/anlogic/demo.adc
 create mode 100644 examples/anlogic/demo.v
 create mode 100644 examples/anlogic/demo.ys

(limited to 'examples')

diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore
new file mode 100644
index 000000000..fa9424cd8
--- /dev/null
+++ b/examples/anlogic/.gitignore
@@ -0,0 +1,4 @@
+demo.bit
+demo_phy.area
+full.v
+*.log
\ No newline at end of file
diff --git a/examples/anlogic/README b/examples/anlogic/README
new file mode 100644
index 000000000..99143cce0
--- /dev/null
+++ b/examples/anlogic/README
@@ -0,0 +1,13 @@
+LED Blink project for Anlogic Lichee Tang board.
+
+Follow the install instructions for the Tang Dynasty IDE from given link below.
+
+https://tang.sipeed.com/en/getting-started/installing-td-ide/linux/
+
+
+set TD_HOME env variable to the full path to the TD <TD Install Directory> as follow.
+
+export TD_HOME=<TD Install Directory>
+
+then run "bash build.sh" in this directory.
+
diff --git a/examples/anlogic/build.sh b/examples/anlogic/build.sh
new file mode 100755
index 000000000..8b77a32d6
--- /dev/null
+++ b/examples/anlogic/build.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+set -ex
+yosys demo.ys
+$TD_HOME/bin/td build.tcl
\ No newline at end of file
diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl
new file mode 100644
index 000000000..db8c3b347
--- /dev/null
+++ b/examples/anlogic/build.tcl
@@ -0,0 +1,11 @@
+import_device eagle_s20.db -package BG256
+read_verilog full.v -top demo
+read_adc demo.adc
+optimize_rtl
+map_macro
+map
+pack
+place
+route
+report_area -io_info -file demo_phy.area
+bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000
diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc
new file mode 100644
index 000000000..c8fbaed3e
--- /dev/null
+++ b/examples/anlogic/demo.adc
@@ -0,0 +1,2 @@
+set_pin_assignment {CLK_IN} { LOCATION = K14;  } ##24MHZ
+set_pin_assignment {R_LED} { LOCATION = R3;  } ##R_LED
\ No newline at end of file
diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v
new file mode 100644
index 000000000..a7edf4e37
--- /dev/null
+++ b/examples/anlogic/demo.v
@@ -0,0 +1,18 @@
+module demo (
+    input wire CLK_IN,  
+    output wire R_LED 
+);
+    parameter time1 = 30'd12_000_000;
+    reg led_state;
+    reg [29:0] count;
+    
+    always @(posedge CLK_IN)begin
+        if(count == time1)begin
+            count<= 30'd0; 	
+            led_state <= ~led_state;
+        end
+        else
+            count <= count + 1'b1;
+    end
+    assign R_LED = led_state;
+endmodule
\ No newline at end of file
diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys
new file mode 100644
index 000000000..5687bcd31
--- /dev/null
+++ b/examples/anlogic/demo.ys
@@ -0,0 +1,3 @@
+read_verilog demo.v
+synth_anlogic -top demo
+write_verilog full.v
\ No newline at end of file
-- 
cgit v1.2.3


From 3ef427f4a96ac8f890cf94079315e172db409526 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 15:21:04 -0800
Subject: Add missing newline

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/anlogic/build.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'examples')

diff --git a/examples/anlogic/build.sh b/examples/anlogic/build.sh
index 8b77a32d6..e0f6b4cfe 100755
--- a/examples/anlogic/build.sh
+++ b/examples/anlogic/build.sh
@@ -1,4 +1,4 @@
 #!/bin/bash
 set -ex
 yosys demo.ys
-$TD_HOME/bin/td build.tcl
\ No newline at end of file
+$TD_HOME/bin/td build.tcl
-- 
cgit v1.2.3


From 24d1b92eda20269da7ee7ae713f3ab92b8865349 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 17:27:58 -0800
Subject: Improve igloo2 exmaple

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.pdc |  7 +++++++
 examples/igloo2/example.sdc |  1 +
 examples/igloo2/example.v   | 12 ++++++------
 examples/igloo2/libero.tcl  |  4 ++--
 4 files changed, 16 insertions(+), 8 deletions(-)

(limited to 'examples')

diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc
index e6ffd53db..0cf34adb3 100644
--- a/examples/igloo2/example.pdc
+++ b/examples/igloo2/example.pdc
@@ -1 +1,8 @@
 # Add placement constraints here
+set_io clk  -pinname H16 -fixed yes -DIRECTION INPUT
+set_io SW1  -pinname H12 -fixed yes -DIRECTION INPUT
+set_io SW2  -pinname H13 -fixed yes -DIRECTION INPUT
+set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT
+set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT
+set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT
+set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT
diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
index c6ff94161..f8b487316 100644
--- a/examples/igloo2/example.sdc
+++ b/examples/igloo2/example.sdc
@@ -1 +1,2 @@
 # Add timing constraints here
+create_clock -period 10.000 -waveform {0.000 5.000} [get_ports {clk}]
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 1a1967d5a..b701c707d 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -1,23 +1,23 @@
 module example (
 	input  clk,
-	input  EN,
+	input  SW1,
+	input  SW2,
 	output LED1,
 	output LED2,
 	output LED3,
-	output LED4,
-	output LED5
+	output LED4
 );
 
-	localparam BITS = 5;
+	localparam BITS = 4;
 	localparam LOG2DELAY = 22;
 
 	reg [BITS+LOG2DELAY-1:0] counter = 0;
 	reg [BITS-1:0] outcnt;
 
 	always @(posedge clk) begin
-		counter <= counter + EN;
+		counter <= counter + SW1 + SW2 + 1;
 		outcnt <= counter >> LOG2DELAY;
 	end
 
-	assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
+	assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
 endmodule
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 6f7d4e24b..abc94e479 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -8,8 +8,8 @@ new_project \
     -block_mode 0 \
     -hdl "VERILOG" \
     -family IGLOO2 \
-    -die PA4MGL500 \
-    -package tq144 \
+    -die PA4MGL2500 \
+    -package vf256 \
     -speed -1
 
 import_files -hdl_source {netlist.vm}
-- 
cgit v1.2.3


From 7c03b0b08209c7e1b3972a05db63b23c0b1d7a5e Mon Sep 17 00:00:00 2001
From: Kali Prasad <kprasadvnsi@pm.me>
Date: Wed, 6 Mar 2019 09:51:11 +0530
Subject: examples/anlogic/ now also output the SVF file.

---
 examples/anlogic/.gitignore |  5 ++++-
 examples/anlogic/README     |  1 -
 examples/anlogic/build.tcl  |  2 +-
 examples/anlogic/demo.adc   |  2 +-
 examples/anlogic/demo.v     | 10 +++++-----
 examples/anlogic/demo.ys    |  2 +-
 6 files changed, 12 insertions(+), 10 deletions(-)

(limited to 'examples')

diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore
index fa9424cd8..97c978a15 100644
--- a/examples/anlogic/.gitignore
+++ b/examples/anlogic/.gitignore
@@ -1,4 +1,7 @@
 demo.bit
 demo_phy.area
 full.v
-*.log
\ No newline at end of file
+*.log
+*.h
+*.tde
+*.svf
diff --git a/examples/anlogic/README b/examples/anlogic/README
index 99143cce0..35d8e9cb1 100644
--- a/examples/anlogic/README
+++ b/examples/anlogic/README
@@ -10,4 +10,3 @@ set TD_HOME env variable to the full path to the TD <TD Install Directory> as fo
 export TD_HOME=<TD Install Directory>
 
 then run "bash build.sh" in this directory.
-
diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl
index db8c3b347..06db525c9 100644
--- a/examples/anlogic/build.tcl
+++ b/examples/anlogic/build.tcl
@@ -8,4 +8,4 @@ pack
 place
 route
 report_area -io_info -file demo_phy.area
-bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000
+bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000
diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc
index c8fbaed3e..ec802502e 100644
--- a/examples/anlogic/demo.adc
+++ b/examples/anlogic/demo.adc
@@ -1,2 +1,2 @@
 set_pin_assignment {CLK_IN} { LOCATION = K14;  } ##24MHZ
-set_pin_assignment {R_LED} { LOCATION = R3;  } ##R_LED
\ No newline at end of file
+set_pin_assignment {R_LED} { LOCATION = R3;  } ##R_LED
diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v
index a7edf4e37..e17db771e 100644
--- a/examples/anlogic/demo.v
+++ b/examples/anlogic/demo.v
@@ -1,18 +1,18 @@
 module demo (
-    input wire CLK_IN,  
-    output wire R_LED 
+    input wire CLK_IN,
+    output wire R_LED
 );
     parameter time1 = 30'd12_000_000;
     reg led_state;
     reg [29:0] count;
-    
+
     always @(posedge CLK_IN)begin
         if(count == time1)begin
-            count<= 30'd0; 	
+            count<= 30'd0;
             led_state <= ~led_state;
         end
         else
             count <= count + 1'b1;
     end
     assign R_LED = led_state;
-endmodule
\ No newline at end of file
+endmodule
diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys
index 5687bcd31..cb396cc2b 100644
--- a/examples/anlogic/demo.ys
+++ b/examples/anlogic/demo.ys
@@ -1,3 +1,3 @@
 read_verilog demo.v
 synth_anlogic -top demo
-write_verilog full.v
\ No newline at end of file
+write_verilog full.v
-- 
cgit v1.2.3


From da5181a3df6ceed96f1762e4cdaec5cbe3ea23db Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 19:49:39 -0800
Subject: Improvements in SF2 flow and demo

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/.gitignore | 1 +
 examples/igloo2/runme.sh   | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

(limited to 'examples')

diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore
index ea58efc9f..33b7182d3 100644
--- a/examples/igloo2/.gitignore
+++ b/examples/igloo2/.gitignore
@@ -1,3 +1,4 @@
 /netlist.edn
 /netlist.vm
+/example.stp
 /proj
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index a08894e0a..838f027db 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 set -ex
-yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
+yosys -p 'synth_sf2 -noclkbuf -top example -edif netlist.edn -vlog netlist.vm' example.v
 export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
 /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
 cp proj/designer/example/export/example.stp .
-- 
cgit v1.2.3


From e22afeae907e6340aac7797f60c309916fd72097 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 20:35:48 -0800
Subject: Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.pdc | 12 ++++++++++++
 examples/igloo2/example.v   | 44 ++++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 54 insertions(+), 2 deletions(-)

(limited to 'examples')

diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc
index 0cf34adb3..298d9e934 100644
--- a/examples/igloo2/example.pdc
+++ b/examples/igloo2/example.pdc
@@ -1,8 +1,20 @@
 # Add placement constraints here
+
 set_io clk  -pinname H16 -fixed yes -DIRECTION INPUT
+
 set_io SW1  -pinname H12 -fixed yes -DIRECTION INPUT
 set_io SW2  -pinname H13 -fixed yes -DIRECTION INPUT
+
 set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT
 set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT
 set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT
 set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT
+
+set_io AA   -pinname L12 -fixed yes -DIRECTION OUTPUT
+set_io AB   -pinname L13 -fixed yes -DIRECTION OUTPUT
+set_io AC   -pinname M13 -fixed yes -DIRECTION OUTPUT
+set_io AD   -pinname N15 -fixed yes -DIRECTION OUTPUT
+set_io AE   -pinname L11 -fixed yes -DIRECTION OUTPUT
+set_io AF   -pinname L14 -fixed yes -DIRECTION OUTPUT
+set_io AG   -pinname N14 -fixed yes -DIRECTION OUTPUT
+set_io CA   -pinname M15 -fixed yes -DIRECTION OUTPUT
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index b701c707d..05b6ced5e 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -5,10 +5,13 @@ module example (
 	output LED1,
 	output LED2,
 	output LED3,
-	output LED4
+	output LED4,
+
+	output AA, AB, AC, AD,
+	output AE, AF, AG, CA
 );
 
-	localparam BITS = 4;
+	localparam BITS = 8;
 	localparam LOG2DELAY = 22;
 
 	reg [BITS+LOG2DELAY-1:0] counter = 0;
@@ -20,4 +23,41 @@ module example (
 	end
 
 	assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
+
+	// seg7enc seg7encinst (
+	// 	.seg({AA, AB, AC, AD, AE, AF, AG}),
+	// 	.dat(CA ? outcnt[3:0] : outcnt[7:4])
+	// );
+
+	assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[7:4]);
+	assign CA = counter[10];
+endmodule
+
+module seg7enc (
+	input [3:0] dat,
+	output [6:0] seg
+);
+	reg [6:0] seg_inv;
+	always @* begin
+		seg_inv = 0;
+		case (dat)
+			4'h0: seg_inv = 7'b 0111111;
+			4'h1: seg_inv = 7'b 0000110;
+			4'h2: seg_inv = 7'b 1011011;
+			4'h3: seg_inv = 7'b 1001111;
+			4'h4: seg_inv = 7'b 1100110;
+			4'h5: seg_inv = 7'b 1101101;
+			4'h6: seg_inv = 7'b 1111101;
+			4'h7: seg_inv = 7'b 0000111;
+			4'h8: seg_inv = 7'b 1111111;
+			4'h9: seg_inv = 7'b 1101111;
+			4'hA: seg_inv = 7'b 1110111;
+			4'hB: seg_inv = 7'b 1111100;
+			4'hC: seg_inv = 7'b 0111001;
+			4'hD: seg_inv = 7'b 1011110;
+			4'hE: seg_inv = 7'b 1111001;
+			4'hF: seg_inv = 7'b 1110001;
+		endcase
+	end
+	assign seg = ~seg_inv;
 endmodule
-- 
cgit v1.2.3


From b1b9edf5cc9e280346ffa0132d570a8ff656eb22 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 20:47:07 -0800
Subject: Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'examples')

diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 05b6ced5e..4a9486e50 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -24,13 +24,14 @@ module example (
 
 	assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
 
+	// assign CA = counter[10];
 	// seg7enc seg7encinst (
 	// 	.seg({AA, AB, AC, AD, AE, AF, AG}),
 	// 	.dat(CA ? outcnt[3:0] : outcnt[7:4])
 	// );
 
-	assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[7:4]);
-	assign CA = counter[10];
+	assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]);
+	assign CA = outcnt[7];
 endmodule
 
 module seg7enc (
-- 
cgit v1.2.3


From 78762316aabf6d6fb55cfd4ab5b5a161a69ba203 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 6 Mar 2019 00:41:02 -0800
Subject: Refactor SF2 iobuf insertion, Add clkint insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/runme.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'examples')

diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index 838f027db..a08894e0a 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 set -ex
-yosys -p 'synth_sf2 -noclkbuf -top example -edif netlist.edn -vlog netlist.vm' example.v
+yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
 export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
 /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
 cp proj/designer/example/export/example.stp .
-- 
cgit v1.2.3


From 539a7f3fbce2f27f0de9a298993b13623c5c8f95 Mon Sep 17 00:00:00 2001
From: Benedikt Tutzer <e1225461@student.tuwien.ac.at>
Date: Wed, 3 Apr 2019 11:24:50 +0200
Subject: Added cell_stats example

---
 examples/python-api/netlist_graph.py | 472 -----------------------------------
 examples/python-api/pass.py          |  32 +++
 examples/python-api/run.sh           |   6 -
 examples/python-api/script.py        |  22 ++
 4 files changed, 54 insertions(+), 478 deletions(-)
 delete mode 100644 examples/python-api/netlist_graph.py
 create mode 100755 examples/python-api/pass.py
 delete mode 100755 examples/python-api/run.sh
 create mode 100755 examples/python-api/script.py

(limited to 'examples')

diff --git a/examples/python-api/netlist_graph.py b/examples/python-api/netlist_graph.py
deleted file mode 100644
index c8da76e3d..000000000
--- a/examples/python-api/netlist_graph.py
+++ /dev/null
@@ -1,472 +0,0 @@
-from libyosys import *
-from scipy.sparse import coo_matrix
-from numpy import savetxt
-
-from enum import Enum
-class NodeType(Enum):
-	GRAPH_CELL = 0
-	GRAPH_PI = 1
-	GRAPH_PO = 2
-	GRAPH_CONST = 3
-	GRAPH_WIRE = 4
-
-class NetlistElement:
-
-	def __init__(self, design, module, name):
-		self.design = design
-		self.module = module
-		self.name = name
-
-class Bit(NetlistElement):
-
-	def __init__(self, bit, design, module, node, port, pos):
-		super().__init__(design, module, IdString("\\__BIT__"))
-		self.bit = bit
-		self.node = node
-		self.port = port
-		self.pos = pos
-
-class Port(NetlistElement):
-
-	def __init__(self, name):
-		super().__init__(None, None, name)
-		self.input = False
-		self.output = False
-		self.bits = []
-
-class Node(NetlistElement):
-
-	def __init__(self, design, module, name, nodeType):
-		super().__init__(design, module, name)
-		self.nodeType = nodeType
-		self.ports = []
-
-	def __lt__(self, other):
-		if isinstance(other, self.__class):
-			if self.type == other.type:
-				return self.name.str() < other.name.str()
-			return self.type < other.type
-		return False
-
-class PyCell(Node):
-
-	def __init__(self, design, module, name, cell):
-		super().__init__(design, module, name, NodeType.GRAPH_CELL)
-		self.cell = cell
-
-class PyWire(Node):
-
-	def __init__(self, design, module, name):
-		super().__init__(design, module, name, NodeType.GRAPH_WIRE)
-
-class NetlistGraph:
-
-	def __init__(self, design, module = None):
-		self.design = design
-		if module != None:
-			self.module = module
-		else:
-			self.module = list(design.modules_.values())[0]
-		self.cells = []
-		self.wires = []
-		self.nodes = []
-		self.node_bits = []
-		self.wire_bits = []
-		self.node_index = {}
-		self.node_bit_index = {}
-		self.wire_bit_index = {}
-
-		self.incoming = None
-		self.outgoing = None
-		self.create()
-
-	def create(self):
-
-		log_header(self.design, "Creating abstract graph representation of "
-				+ "module " + self.module.name.str() + "\n")
-		log_push()
-
-		sigmap = SigMap(self.module)
-		
-		log("  Creating const node\n")
-		const_node = Node(self.design, self.module, IdString("\\__CONST__"), NodeType.GRAPH_CONST)
-		const_port = Port(IdString("\\__CONST__"))
-		const_port.input = False
-		const_port.output = True
-		cb = SigBit(State.Sx)
-		const_bit = Bit(cb, self.design, self.module, const_node, const_port, 0)
-		const_node.ports.append(const_port)
-		const_port.bits.append(const_bit)
-
-		self.nodes.append(const_node)
-		self.wires.append(const_node)
-		log("  Creating cell nodes\n")
-
-		for cell in self.module.selected_cells():
-			c = PyCell(self.design, self.module, cell.name, cell)
-			for first, second in cell.connections_.items():
-				p = Port(first)
-				p.input = cell.input(p.name)
-				p.output = cell.output(p.name)
-				for bit in sigmap(second).to_sigbit_vector():
-					b = Bit(bit, self.design, self.module, c, p, len(p.bits))
-					p.bits.append(b)
-				c.ports.append(p)
-
-			self.cells.append(c)
-
-		log("  Creating wire nodes\n")
-
-		for wire in self.module.selected_wires():
-			node = PyWire(self.design, self.module, wire.name)
-			p = Port(IdString(""))
-			if wire.port_input:
-				node.nodeType = NodeType.GRAPH_PI
-				p.name = IdString("\\PI")
-				p.input = False
-				p.output = True
-			elif wire.port_output:
-				node.nodeType = NodeType.GRAPH_PO
-				p.name = IdString("\\PO")
-				p.input = True
-				p.output = False
-			for bit in sigmap(wire).to_sigbit_set():
-				b = Bit(bit, self.design, self.module, node, p, len(p.bits))
-				p.bits.append(b)
-			node.ports.append(p)
-			self.wires.append(node)
-
-		self.nodes.extend(self.cells)
-		self.nodes.extend(wire for wire in self.wires if wire.nodeType in [NodeType.GRAPH_PI, NodeType.GRAPH_PO])
-
-		log("  Creating node index for fast lookup\n")
-
-		idx = 0
-
-		for node in self.nodes:
-			self.node_index[node.name] = idx
-			idx += 1
-
-		log("  Creating node bits (= const + cell + PI + PO)\n")
-
-		for node in self.nodes:
-			for port in node.ports:
-				for bit in port.bits:
-					self.node_bits.append(bit)
-
-		log("  Creating wire bits\n")
-
-		for wire in self.wires:
-			for port in wire.ports:
-				for bit in port.bits:
-					self.wire_bits.append(bit)
-
-		log("  Creating node bit index for fast lookup\n")
-
-		idx = 0
-
-		for bit in self.node_bits:
-			self.node_bit_index[bit] = idx
-			idx += 1
-
-		log("  Creating wire bit index for fast lookup\n")
-
-		idx = 0
-
-		for bit in self.wire_bits:
-			self.wire_bit_index[bit] = idx
-			idx += 1
-
-		log("  Mapping port.wire connections to wire bit index\n")
-
-		idx = 0
-
-		wbitmap = {}
-		for wbit in self.wire_bits:
-			wbitmap[wbit.bit] = idx
-			idx += 1
-
-		inputTriplets = []
-		outputTriplets = [(0,0,1)]
-
-		log("  Mapping node bits to wire bits\n")
-
-		idx = 0
-
-		for nbit in self.node_bits:
-			row = idx
-			idx += 1
-			col = 0
-			val = 1
-
-			def check_wire():
-				nonlocal nbit
-				try:
-					wire = nbit.bit.wire
-					return True
-				except:
-					return False
-
-			if check_wire() and not self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
-				continue
-
-			if check_wire():
-				col = wbitmap[nbit.bit]
-
-			triplet = (row, col, val)
-
-			if col == 0 and row != 0:
-				inputTriplets.append(triplet)
-				continue
-
-			if nbit.node.nodeType == NodeType.GRAPH_CELL:
-				cell = nbit.node
-				if check_wire() and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
-					if cell.cell.input(nbit.port.name):
-						inputTriplets.append(triplet)
-					if cell.cell.output(nbit.port.name):
-						outputTriplets.append(triplet)
-				continue
-
-			if nbit.node.nodeType == NodeType.GRAPH_PI and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
-				outputTriplets.append(triplet)
-				continue
-
-			if nbit.node.nodeType == NodeType.GRAPH_PO and self.design.selected_member(self.module.name, self.module.wire(nbit.bit.wire.name).name):
-				inputTriplets.append(triplet)
-				continue
-
-		log("  Creating port-to-wire incidence matrices\n")
-
-		sizeX = len(self.node_bits)
-		sizeY= len(self.wire_bits)
-
-		inputRows = [i[0] for i in inputTriplets]
-		inputCols = [i[1] for i in inputTriplets]
-		inputVals = [i[2] for i in inputTriplets]
-		self.incoming = coo_matrix((inputVals, (inputRows, inputCols)), shape=(sizeX, sizeY), dtype='int32')
-
-		outputRows = [i[0] for i in outputTriplets]
-		outputCols = [i[1] for i in outputTriplets]
-		outputVals = [i[2] for i in outputTriplets]
-		self.outgoing = coo_matrix((outputVals, (outputRows, outputCols)), shape=(sizeX, sizeY), dtype='int32')
-
-	def dot(self):
-		log_header(self.design, "Creating 'dot' bipartite module graph representation of module " + self.module.name.str() + "\n")
-		log_push()
-		bitmap = {}
-
-		ss  = "digraph g{\n"
-		ss += "  rankdir = LR\n"
-		nidx = 0
-		pidx = 0
-		bidx = 0
-		cells_wires = []
-		cells_wires.extend(self.cells)
-		cells_wires.extend(self.wires)
-
-		idx = 0
-
-		for node in cells_wires:
-			for port in node.ports:
-				for bit in port.bits:
-					bitmap[bit] = idx
-					idx += 1
-		
-		for node in cells_wires:
-			ss += "  subgraph cluster" + str(nidx) + " {\n"
-			ss += "    style = \"setlinewidth(2)\";\n"
-			ss += "    margin = .2;\n"
-			ss += "    n" + str(node.name.index_)
-
-			def s_cell():
-				nonlocal ss
-				ss += "[shape=ellipse,label=\"" + str(nidx) + ":"
-				ss += unescape_id(node.cell.type) + "\""
-			def s_pi():
-				nonlocal ss
-				ss += "[shape = box, label=\"" + str(nidx) + ":"
-				ss += unescape_id(node.name.str()) + "\""
-			def s_po():
-				nonlocal ss
-				ss += "[shape = diamond, label=\"" + str(nidx) + ":"
-				ss += unescape_id(node.name.str()) + "\""
-			def s_const():
-				nonlocal ss
-				ss += "[shape = octagon, label=\"" + str(nidx) + ":CO\""
-			def s_wire():
-				nonlocal ss
-				ss += "[shape = plaintext, label=\"" + str(nidx - len(self.cells)) + ":"
-				ss += unescape_id(node.name.str()) + "\""
-			switch = {
-					NodeType.GRAPH_CELL : s_cell,
-					NodeType.GRAPH_PI : s_pi,
-					NodeType.GRAPH_PO : s_po,
-					NodeType.GRAPH_CONST : s_const,
-					NodeType.GRAPH_WIRE : s_wire
-					}
-			switch[node.nodeType]()
-
-			ss += "];\n"
-
-			pidx = 0
-			for port in node.ports:
-				ss += "    port_" + str(node.name.index_) + "_" + str(port.name.index_)
-				ss += "[shape=none,label=<\n"
-				ss += "      <table border=\"0\" cellborder=\"1\" cellspacing=\"0\" cellpadding=\"4\" >\n"
-				ss += "        <tr><td bgcolor=\"lightgray\" port=\"p" + str(node.name.index_) + "_"
-				ss += str(port.name.index_) + "\"> "
-				ss += unescape_id(port.name.str())
-				ss += "</td></tr>\n"
-	
-				bidx = 0;
-				for bit in port.bits:
-
-					ss += "          <tr><td bgcolor=\"white\" port=\"b" + str(node.name.index_) + "_" + str(port.name.index_) + "_" + str(bit.pos) + "\"> " + str(bitmap[bit]) + ":"  + str(bidx) + "</td></tr>\n"
-
-					bidx += 1
-
-				ss += "      </table>\n    >];\n"
-
-				if node.nodeType == NodeType.GRAPH_CELL:
-					if node.cell.output(port.name):
-						ss += "    n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n"
-					else:
-						ss += "    port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) +  ";\n"
-				if node.nodeType == NodeType.GRAPH_PI or node.nodeType == NodeType.GRAPH_CONST:
-					ss += "    n" + str(node.name.index_) + " -> " + "port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + ";\n"
-				if node.nodeType == NodeType.GRAPH_PO:
-					ss += "    port_" + str(node.name.index_) + "_" + str(port.name.index_) + ":p" + str(node.name.index_) + "_" + str(port.name.index_) + " -> " + "n" + str(node.name.index_) +  ";\n"
-
-				pidx += 1
-			ss += "  }\n"
-			nidx += 1
-
-		for i in range(len(self.incoming.nonzero()[0])):
-			b1 = self.node_bits[self.incoming.nonzero()[0][i]]
-			b2 = self.wire_bits[self.incoming.nonzero()[1][i]]
-
-			if b1.node.nodeType == NodeType.GRAPH_PO or b1.node.nodeType == NodeType.GRAPH_CONST:
-				continue
-
-			ss += "  "
-			ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":"
-			ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos)
-			ss += " -> "
-			ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":"
-			ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos)
-			ss += ";\n"
-
-		for i in range(len(self.outgoing.nonzero()[0])):
-			b1 = self.node_bits[self.outgoing.nonzero()[0][i]]
-			b2 = self.wire_bits[self.outgoing.nonzero()[1][i]]
-
-			if b1.node.nodeType == NodeType.GRAPH_PI:
-				continue
-
-			ss += "  "
-			ss += "port_" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + ":"
-			ss += "b" + str(b1.node.name.index_) + "_" + str(b1.port.name.index_) + "_" + str(b1.pos)
-			ss += " -> "
-			ss += "port_" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + ":"
-			ss += "b" + str(b2.node.name.index_) + "_" + str(b2.port.name.index_) + "_" + str(b2.pos)
-			ss += ";\n"
-
-		ss += "}\n"
-
-		log_pop()
-
-		return ss
-
-	def save_dot(self, filename):
-		savetxt(filename, [self.dot()], fmt="%s")
-
-	def save_incoming(self, filename, delimiter = ","):
-		savetxt(filename, self.incoming.todense(), "%d", delimiter=delimiter)
-
-	def save_outgoing(self, filename, delimiter = ","):
-		savetxt(filename, self.outgoing.todense(), "%d", delimiter=delimiter)
-
-	def save_adjacency(self, filename, delimiter = ","):
-		savetxt(filename, (self.outgoing*self.incoming.transpose()).todense(), "%d", delimiter=delimiter)
-
-p = None
-
-class NetlistGraphPass(Pass):
-
-	def __init__(self):
-		super().__init__("netlist_graph", "Generates the Netlist-Graph of a module")
-
-		import argparse
-		self.parser = argparse.ArgumentParser()
-
-		self.parser.add_argument("-mod", nargs=1, metavar="MOD", help="The Netlist-Graph of the module with the id-string <module> will be generated. If this argument is not given, the first module will be used")
-		self.parser.add_argument("-dot", nargs=1, metavar="FILE", help="Write the Netlist-Graph to FILE in dot format")
-		self.parser.add_argument("-i","-incoming", nargs=1, metavar="FILE", help="Write the incoming incidence matrix to FILE in csv format")
-		self.parser.add_argument("-o","-outgoing", nargs=1, metavar="FILE", help="Write the outgoing incidence matrix to FILE in csv format")
-		self.parser.add_argument("-a","-adjacency", nargs=1, metavar="FILE", help="Write the adjacency matrix to FILE in csv format")
-
-	def py_help(self):
-
-		log("This pass generates the Netlist-Graph of a module\n")
-		log(self.parser.format_help())
-
-	def py_execute(self, args, des):
-
-		args = self.parser.parse_args(args[1:])
-
-		graph = None
-		if args.mod:
-			try:
-				graph = NetlistGraph(des, des.modules_[IdString(args.mod[0])])
-			except KeyError:
-				log("Module \"" + args.mod[0] + "\" not found!\n")
-				exit()
-		else:
-			graph = NetlistGraph(des, list(des.modules_.values())[0])
-
-		if args.dot:
-			graph.save_dot(args.dot[0])
-
-		if args.i:
-			graph.save_incoming(args.i[0])
-
-		if args.o:
-			graph.save_outgoing(args.o[0])
-
-		if args.a:
-			graph.save_adjacency(args.a[0])
-	
-	def py_clear_flags(self):
-		log("Clear\n")
-
-if __name__ == "__main__":
-
-	designs = {}
-	graphs = {}
-
-	testdir = "../../tests/simple/"
-
-	import os
-	for testcase in os.listdir(testdir):
-		if not testcase.endswith(".v"):
-			continue
-		designs[testcase] = Design()
-		run_pass("read_verilog " + testdir + testcase, designs[testcase])
-		run_pass("hierarchy -check -auto-top", designs[testcase])
-		run_pass("proc", designs[testcase])
-		run_pass("clean", designs[testcase])
-		run_pass("memory", designs[testcase])
-		run_pass("clean", designs[testcase])
-		run_pass("opt -full", designs[testcase])
-		run_pass("clean", designs[testcase])
-		graphs[testcase] = NetlistGraph(designs[testcase])
-
-		file_prefix = "out/" + testcase
-		graphs[testcase].save_dot(file_prefix + ".dot")
-		graphs[testcase].save_incoming(file_prefix + "_in.csv")
-		graphs[testcase].save_outgoing(file_prefix + "_out.csv")
-		graphs[testcase].save_adjacency(file_prefix + "_adjacency.csv")
-
-else:
-	p = NetlistGraphPass()
diff --git a/examples/python-api/pass.py b/examples/python-api/pass.py
new file mode 100755
index 000000000..d67cf4a23
--- /dev/null
+++ b/examples/python-api/pass.py
@@ -0,0 +1,32 @@
+#!/usr/bin/python3
+
+from pyosys import libyosys as ys
+
+import matplotlib.pyplot as plt
+import numpy as np
+
+class CellStatsPass(ys.Pass):
+
+    def __init__(self):
+        super().__init__("cell_stats", "Shows cell stats as plot")
+
+    def py_help(self):
+        ys.log("This pass uses the matplotlib library to display cell stats\n")
+
+    def py_execute(self, args, design):
+        ys.log_header(design, "Plotting cell stats\n")
+        cell_stats = {}
+        for module in design.selected_whole_modules_warn():
+            for cell in module.selected_cells():
+                if cell.type.str() in cell_stats:
+                    cell_stats[cell.type.str()] += 1
+                else:
+                    cell_stats[cell.type.str()] = 1
+        plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center')
+        plt.xticks(range(len(cell_stats)), list(cell_stats.keys()))
+        plt.show()
+
+    def py_clear_flags(self):
+        ys.log("Clear Flags - CellStatsPass\n")
+
+p = CellStatsPass()
diff --git a/examples/python-api/run.sh b/examples/python-api/run.sh
deleted file mode 100755
index 5852ea9ac..000000000
--- a/examples/python-api/run.sh
+++ /dev/null
@@ -1,6 +0,0 @@
-PYTHONPATH=`pwd`/../../:$PYTHONPATH
-mkdir -p out
-if [ ! -f ../../libyosys.so ]; then
-	make -C ../..
-fi
-python3.5 netlist_graph.py
diff --git a/examples/python-api/script.py b/examples/python-api/script.py
new file mode 100755
index 000000000..f0fa5a0b8
--- /dev/null
+++ b/examples/python-api/script.py
@@ -0,0 +1,22 @@
+#!/usr/bin/python3
+
+from pyosys import libyosys as ys
+
+import matplotlib.pyplot as plt
+import numpy as np
+
+design = ys.Design()
+ys.run_pass("read_verilog ../../tests/simple/fiedler-cooley.v", design);
+ys.run_pass("prep", design)
+ys.run_pass("opt -full", design)
+
+cell_stats = {}
+for module in design.selected_whole_modules_warn():
+  for cell in module.selected_cells():
+    if cell.type.str() in cell_stats:
+      cell_stats[cell.type.str()] += 1
+    else:
+      cell_stats[cell.type.str()] = 1
+plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center')
+plt.xticks(range(len(cell_stats)), list(cell_stats.keys()))
+plt.show()
-- 
cgit v1.2.3


From 173c97589471b5f4312acac4e396a250ee7158c1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <marcin@symbioticeda.com>
Date: Wed, 24 Jul 2019 18:41:39 +0200
Subject: Add a simple example for Spartan 6

---
 examples/mimas2/README       |  8 ++++++++
 examples/mimas2/example.ucf  | 13 +++++++++++++
 examples/mimas2/example.v    | 14 ++++++++++++++
 examples/mimas2/run.sh       |  8 ++++++++
 examples/mimas2/run_yosys.ys |  4 ++++
 5 files changed, 47 insertions(+)
 create mode 100644 examples/mimas2/README
 create mode 100644 examples/mimas2/example.ucf
 create mode 100644 examples/mimas2/example.v
 create mode 100644 examples/mimas2/run.sh
 create mode 100644 examples/mimas2/run_yosys.ys

(limited to 'examples')

diff --git a/examples/mimas2/README b/examples/mimas2/README
new file mode 100644
index 000000000..b12875cbc
--- /dev/null
+++ b/examples/mimas2/README
@@ -0,0 +1,8 @@
+A simple example design, based on the Numato Labs Mimas V2 board
+================================================================
+
+This example uses Yosys for synthesis and Xilinx ISE
+for place&route and bit-stream creation.
+
+To synthesize:
+  bash run.sh
diff --git a/examples/mimas2/example.ucf b/examples/mimas2/example.ucf
new file mode 100644
index 000000000..4e31b74ab
--- /dev/null
+++ b/examples/mimas2/example.ucf
@@ -0,0 +1,13 @@
+CONFIG VCCAUX = "3.3" ;
+
+
+NET "CLK"                   LOC = D9      | IOSTANDARD = LVCMOS33 | PERIOD = 12MHz ;
+
+NET "LED[7]"                     LOC = P15     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[6]"                     LOC = P16     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[5]"                     LOC = N15     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[4]"                     LOC = N16     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[3]"                     LOC = U17     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[2]"                     LOC = U18     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[1]"                     LOC = T17     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "LED[0]"                     LOC = T18     | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
diff --git a/examples/mimas2/example.v b/examples/mimas2/example.v
new file mode 100644
index 000000000..2a9117393
--- /dev/null
+++ b/examples/mimas2/example.v
@@ -0,0 +1,14 @@
+module example(
+	input wire CLK,
+	output wire [7:0] LED
+);
+
+reg [27:0] ctr;
+initial ctr = 0;
+
+always @(posedge CLK)
+	ctr <= ctr + 1;
+
+assign LED = ctr[27:20];
+
+endmodule
diff --git a/examples/mimas2/run.sh b/examples/mimas2/run.sh
new file mode 100644
index 000000000..aafde78ed
--- /dev/null
+++ b/examples/mimas2/run.sh
@@ -0,0 +1,8 @@
+#!/bin/sh
+set -e
+yosys run_yosys.ys
+edif2ngd example.edif
+ngdbuild example -uc example.ucf -p xc6slx9csg324-3
+map -w example
+par -w example.ncd example_par.ncd
+bitgen -w example_par.ncd -g StartupClk:JTAGClk
diff --git a/examples/mimas2/run_yosys.ys b/examples/mimas2/run_yosys.ys
new file mode 100644
index 000000000..b3204b1ca
--- /dev/null
+++ b/examples/mimas2/run_yosys.ys
@@ -0,0 +1,4 @@
+read_verilog example.v
+synth_xilinx -top example -family xc6s
+iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
+write_edif -pvector bra example.edif
-- 
cgit v1.2.3


From f4c62f33ac56bc5725c44ad822e75d2387f98061 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Mon, 12 Aug 2019 15:57:43 +0000
Subject: Add clock buffer insertion pass, improve iopadmap.

A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
---
 examples/mimas2/run_yosys.ys | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'examples')

diff --git a/examples/mimas2/run_yosys.ys b/examples/mimas2/run_yosys.ys
index b3204b1ca..b48877811 100644
--- a/examples/mimas2/run_yosys.ys
+++ b/examples/mimas2/run_yosys.ys
@@ -1,4 +1,3 @@
 read_verilog example.v
-synth_xilinx -top example -family xc6s
-iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
+synth_xilinx -top example -family xc6s -ise
 write_edif -pvector bra example.edif
-- 
cgit v1.2.3