From c27dcc1e47fa00cd415893c9d3f637a5d5865988 Mon Sep 17 00:00:00 2001
From: dh73 <dh73_fpga@qq.com>
Date: Wed, 5 Apr 2017 23:01:29 -0500
Subject: Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs

---
 examples/intel/MAX10/runme_postsynth | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 examples/intel/MAX10/runme_postsynth

(limited to 'examples/intel/MAX10/runme_postsynth')

diff --git a/examples/intel/MAX10/runme_postsynth b/examples/intel/MAX10/runme_postsynth
new file mode 100644
index 000000000..f16210540
--- /dev/null
+++ b/examples/intel/MAX10/runme_postsynth
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
+vvp -N verif_post
+
-- 
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